GPIO Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.270s	55.973us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.280s	377.586us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.280s	99.472us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.370s	98.976us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.620s	24.904us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.570s	35.149us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.150s	179.958us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.760s	67.036us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.250s	28.059us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.570s	35.149us	20	20	100.00
		gpio_csr_aliasing	0.760s	67.036us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.220s	281.636us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.120s	61.505us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.860s	39.930us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.220s	88.505us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.060s	258.321us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.140s	99.110us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	23.000s	5.665ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	5.280s	393.403us	50	50	100.00
V2	full_random	gpio_full_random	0.910s	128.450us	50	50	100.00
V2	stress_all	gpio_stress_all	2.919m	8.419ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	42.834us	50	50	100.00
V2	intr_test	gpio_intr_test	0.620s	48.147us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.180s	66.431us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.180s	66.431us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.570s	35.149us	20	20	100.00
		gpio_same_csr_outstanding	0.750s	151.890us	20	20	100.00
		gpio_csr_aliasing	0.760s	67.036us	5	5	100.00
		gpio_csr_hw_reset	0.620s	24.904us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.570s	35.149us	20	20	100.00
		gpio_same_csr_outstanding	0.750s	151.890us	20	20	100.00
		gpio_csr_aliasing	0.760s	67.036us	5	5	100.00
		gpio_csr_hw_reset	0.620s	24.904us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.380s	125.483us	20	20	100.00
		gpio_sec_cm	0.870s	99.260us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.380s	125.483us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	3.886m	7.928ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			940	970	96.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
  • Test gpio_stress_all_with_rand_reset has 30 failures.

    • 1.gpio_stress_all_with_rand_reset.101969534316298816797053748349151093469688035650158235155385970005523887931920
      Line 453, in log /workspaces/repo/scratch/os_regression_2024_08_22/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2907545671 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2907545671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.106578681938271140111472712107427974178862410928895348663821356323669034989781
      Line 485, in log /workspaces/repo/scratch/os_regression_2024_08_22/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3702603333 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3702603333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.

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