GPIO Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	2.320s	190.758us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	2.210s	78.598us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.630s	458.867us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.660s	95.602us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.970s	91.328us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.910s	125.536us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.610s	986.628us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	1.260s	78.027us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	2.200s	57.071us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.910s	125.536us	20	20	100.00
		gpio_csr_aliasing	1.260s	78.027us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.830s	37.623us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.860s	628.658us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.410s	100.875us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	2.180s	120.730us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	5.700s	185.838us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	5.000s	92.732us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	44.510s	2.053ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	7.950s	953.944us	50	50	100.00
V2	full_random	gpio_full_random	1.730s	110.828us	50	50	100.00
V2	stress_all	gpio_stress_all	3.780m	31.916ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.900s	16.900us	50	50	100.00
V2	intr_test	gpio_intr_test	0.910s	26.528us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.290s	161.289us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.290s	161.289us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.910s	125.536us	20	20	100.00
		gpio_same_csr_outstanding	1.190s	18.611us	20	20	100.00
		gpio_csr_aliasing	1.260s	78.027us	5	5	100.00
		gpio_csr_hw_reset	0.970s	91.328us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.910s	125.536us	20	20	100.00
		gpio_same_csr_outstanding	1.190s	18.611us	20	20	100.00
		gpio_csr_aliasing	1.260s	78.027us	5	5	100.00
		gpio_csr_hw_reset	0.970s	91.328us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.950s	114.737us	20	20	100.00
		gpio_sec_cm	1.440s	59.519us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.950s	114.737us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	3.742m	15.125ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			937	970	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
  • Test gpio_stress_all_with_rand_reset has 33 failures.

    • 1.gpio_stress_all_with_rand_reset.32074873365083722299781255817549353962396584081108611876566367507864951344691
      Line 156, in log /workspaces/repo/scratch/os_regression_2024_08_26/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1720698870 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1720698870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.35824629461049221316695940887543807254952460115317286866135388477444843504219
      Line 824, in log /workspaces/repo/scratch/os_regression_2024_08_26/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5710974953 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5710974953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 31 more failures.

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