GPIO Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 2.400s 984.750us 50 50 100.00
gpio_smoke_no_pullup_pulldown 2.430s 356.153us 50 50 100.00
gpio_smoke_en_cdc_prim 1.740s 76.576us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.990s 313.003us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.970s 49.364us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.920s 16.593us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 4.610s 389.796us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 1.150s 152.453us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 2.160s 70.737us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.920s 16.593us 20 20 100.00
gpio_csr_aliasing 1.150s 152.453us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 2.240s 56.670us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 2.270s 252.274us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.520s 72.158us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 2.550s 106.529us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 5.610s 153.915us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 6.290s 96.406us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 39.870s 570.556us 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 10.530s 551.577us 50 50 100.00
V2 full_random gpio_full_random 1.710s 98.567us 50 50 100.00
V2 stress_all gpio_stress_all 5.710m 45.092ms 50 50 100.00
V2 alert_test gpio_alert_test 0.920s 14.259us 50 50 100.00
V2 intr_test gpio_intr_test 0.900s 52.122us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.950s 694.061us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.950s 694.061us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.920s 16.593us 20 20 100.00
gpio_same_csr_outstanding 1.340s 134.115us 20 20 100.00
gpio_csr_aliasing 1.150s 152.453us 5 5 100.00
gpio_csr_hw_reset 0.970s 49.364us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.920s 16.593us 20 20 100.00
gpio_same_csr_outstanding 1.340s 134.115us 20 20 100.00
gpio_csr_aliasing 1.150s 152.453us 5 5 100.00
gpio_csr_hw_reset 0.970s 49.364us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 2.030s 1.178ms 20 20 100.00
gpio_sec_cm 1.550s 453.842us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 2.030s 1.178ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 4.608m 6.996ms 16 50 32.00
V3 TOTAL 16 50 32.00
TOTAL 936 970 96.49

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results