GPIO Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	2.290s	358.747us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	2.270s	89.157us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.850s	67.778us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.940s	332.964us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	1.050s	19.734us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.970s	18.883us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	4.270s	263.708us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	1.290s	32.703us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	2.200s	123.687us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.970s	18.883us	20	20	100.00
		gpio_csr_aliasing	1.290s	32.703us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	2.170s	147.291us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.950s	127.181us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.490s	87.594us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	2.120s	185.831us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	5.720s	498.478us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	5.190s	181.623us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	34.500s	600.243us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	8.280s	332.521us	50	50	100.00
V2	full_random	gpio_full_random	1.650s	88.047us	50	50	100.00
V2	stress_all	gpio_stress_all	3.630m	16.746ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.910s	16.459us	50	50	100.00
V2	intr_test	gpio_intr_test	0.960s	44.635us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	4.190s	513.741us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	4.190s	513.741us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.970s	18.883us	20	20	100.00
		gpio_same_csr_outstanding	1.390s	35.569us	20	20	100.00
		gpio_csr_aliasing	1.290s	32.703us	5	5	100.00
		gpio_csr_hw_reset	1.050s	19.734us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.970s	18.883us	20	20	100.00
		gpio_same_csr_outstanding	1.390s	35.569us	20	20	100.00
		gpio_csr_aliasing	1.290s	32.703us	5	5	100.00
		gpio_csr_hw_reset	1.050s	19.734us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	2.340s	119.802us	20	20	100.00
		gpio_sec_cm	2.050s	260.180us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	2.340s	119.802us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	3.798m	12.540ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			939	970	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
- Test gpio_stress_all_with_rand_reset has 31 failures.
  - 0.gpio_stress_all_with_rand_reset.56711958308271175216902134949802432150000644338327947531155306117715758666910
    Line 244, in log /workspaces/repo/scratch/os_regression_2024_08_31/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 640026263 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 640026263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.gpio_stress_all_with_rand_reset.97783497942780907933272837101594760406972887301707721705983333869311558607946
    Line 348, in log /workspaces/repo/scratch/os_regression_2024_08_31/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 900389059 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 900389059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.

GPIO Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ed1c41cd0f`