GPIO Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	2.290s	300.533us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	2.320s	52.536us	50	50	100.00
		gpio_smoke_en_cdc_prim	2.180s	125.223us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.710s	135.987us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.970s	47.518us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.960s	28.241us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	4.130s	324.020us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	1.250s	19.363us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	2.330s	122.762us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.960s	28.241us	20	20	100.00
		gpio_csr_aliasing	1.250s	19.363us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	2.000s	76.298us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	2.140s	1.054ms	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.450s	45.495us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	2.210s	91.922us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	5.160s	149.986us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	5.340s	90.385us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	39.410s	2.251ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	9.480s	10.584ms	50	50	100.00
V2	full_random	gpio_full_random	1.740s	403.330us	50	50	100.00
V2	stress_all	gpio_stress_all	4.178m	7.549ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.910s	46.871us	50	50	100.00
V2	intr_test	gpio_intr_test	0.950s	16.774us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.680s	58.940us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.680s	58.940us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.960s	28.241us	20	20	100.00
		gpio_same_csr_outstanding	1.300s	72.658us	20	20	100.00
		gpio_csr_aliasing	1.250s	19.363us	5	5	100.00
		gpio_csr_hw_reset	0.970s	47.518us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.960s	28.241us	20	20	100.00
		gpio_same_csr_outstanding	1.300s	72.658us	20	20	100.00
		gpio_csr_aliasing	1.250s	19.363us	5	5	100.00
		gpio_csr_hw_reset	0.970s	47.518us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	2.170s	421.411us	20	20	100.00
		gpio_sec_cm	1.550s	89.876us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	2.170s	421.411us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	3.339m	5.389ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			935	970	96.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
  • Test gpio_stress_all_with_rand_reset has 35 failures.

    • 0.gpio_stress_all_with_rand_reset.42520472976026674516387735970941109810324438082903623928749066632658207813977
      Line 245, in log /workspaces/repo/scratch/os_regression_2024_09_03/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1175738125 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1175738125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.101990133127447628022662016486462876796203912013676509264869712162865703652357
      Line 1015, in log /workspaces/repo/scratch/os_regression_2024_09_03/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18251920318 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 18251920318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 33 more failures.

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