GPIO Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 2.490s 438.204us 50 50 100.00
gpio_smoke_no_pullup_pulldown 2.760s 76.203us 50 50 100.00
gpio_smoke_en_cdc_prim 1.930s 317.516us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.950s 101.624us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.970s 58.010us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.940s 12.529us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 5.140s 1.476ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 1.230s 144.231us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.790s 110.317us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.940s 12.529us 20 20 100.00
gpio_csr_aliasing 1.230s 144.231us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 2.480s 72.738us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 2.210s 33.149us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.500s 107.390us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 2.590s 109.288us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 6.420s 124.511us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 6.990s 94.803us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 42.560s 1.830ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 9.090s 837.699us 50 50 100.00
V2 full_random gpio_full_random 1.760s 85.003us 50 50 100.00
V2 stress_all gpio_stress_all 3.571m 28.271ms 50 50 100.00
V2 alert_test gpio_alert_test 0.920s 16.246us 50 50 100.00
V2 intr_test gpio_intr_test 0.920s 45.034us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.870s 133.435us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.870s 133.435us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.940s 12.529us 20 20 100.00
gpio_same_csr_outstanding 1.170s 39.349us 20 20 100.00
gpio_csr_aliasing 1.230s 144.231us 5 5 100.00
gpio_csr_hw_reset 0.970s 58.010us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.940s 12.529us 20 20 100.00
gpio_same_csr_outstanding 1.170s 39.349us 20 20 100.00
gpio_csr_aliasing 1.230s 144.231us 5 5 100.00
gpio_csr_hw_reset 0.970s 58.010us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 2.120s 1.660ms 20 20 100.00
gpio_sec_cm 1.450s 300.053us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 2.120s 1.660ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 3.928m 33.923ms 19 50 38.00
V3 TOTAL 19 50 38.00
TOTAL 939 970 96.80

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results