GPIO Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.870s 170.842us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.910s 319.427us 50 50 100.00
gpio_smoke_en_cdc_prim 41.621s 47 50 94.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 35.017s 48 50 96.00
V1 csr_hw_reset gpio_csr_hw_reset 0.990s 48.802us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.880s 45.207us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.850s 372.402us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 1.230s 43.085us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.800s 79.402us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.880s 45.207us 20 20 100.00
gpio_csr_aliasing 1.230s 43.085us 5 5 100.00
V1 TOTAL 250 255 98.04
V2 direct_and_masked_out gpio_random_dout_din 2.090s 527.756us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.910s 76.489us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 22.408s 49 50 98.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 35.554s 49 50 98.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 4.240s 386.767us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 35.496s 49 50 98.00
V2 noise_filter_stress gpio_filter_stress 35.465s 49 50 98.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 35.436s 49 50 98.00
V2 full_random gpio_full_random 35.408s 48 50 96.00
V2 stress_all gpio_stress_all 3.374m 33.453ms 48 50 96.00
V2 alert_test gpio_alert_test 23.024s 48 50 96.00
V2 intr_test gpio_intr_test 25.961s 47 50 94.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.220s 498.180us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.220s 498.180us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.880s 45.207us 20 20 100.00
gpio_same_csr_outstanding 1.150s 180.680us 20 20 100.00
gpio_csr_aliasing 1.230s 43.085us 5 5 100.00
gpio_csr_hw_reset 0.990s 48.802us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.880s 45.207us 20 20 100.00
gpio_same_csr_outstanding 1.150s 180.680us 20 20 100.00
gpio_csr_aliasing 1.230s 43.085us 5 5 100.00
gpio_csr_hw_reset 0.990s 48.802us 5 5 100.00
V2 TOTAL 626 640 97.81
V2S tl_intg_err gpio_tl_intg_err 26.012s 19 20 95.00
gpio_sec_cm 0.930s 286.726us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 26.012s 19 20 95.00
V2S TOTAL 24 25 96.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 3.337m 23.786ms 18 50 36.00
V3 TOTAL 18 50 36.00
TOTAL 918 970 94.64

Testplan Progress

Items Total Written Passing Progress
V1 9 9 7 77.78
V2 14 14 5 35.71
V2S 2 2 1 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results