69c572b503| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 8.070s | 655.680us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.000s | 45.062us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 1.000s | 135.718us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 16.550s | 1.056ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.850s | 444.241us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 12.829m | 208.706ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 1.000s | 135.718us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.850s | 444.241us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.257m | 16.551ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.201m | 4.434ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.190m | 31.052ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.450s | 71.977us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.116m | 2.773ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 26.357m | 18.426ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 7.323m | 10.590ms | 9 | 50 | 18.00 |
| V2 | wipe_secret | hmac_wipe_secret | 19.970s | 6.411ms | 4 | 50 | 8.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 38.569m | 314.381ms | 15 | 50 | 30.00 |
| V2 | alert_test | hmac_alert_test | 0.660s | 56.635us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.660s | 33.642us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.010s | 79.703us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.010s | 79.703us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.000s | 45.062us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.000s | 135.718us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.850s | 444.241us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.430s | 621.590us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.000s | 45.062us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.000s | 135.718us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.850s | 444.241us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.430s | 621.590us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 468 | 590 | 79.32 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.460s | 880.213us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.420s | 220.619us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.420s | 220.619us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 8.070s | 655.680us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.057h | 198.365ms | 2 | 200 | 1.00 |
| V3 | TOTAL | 2 | 200 | 1.00 | |||
| TOTAL | 600 | 920 | 65.22 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 10 | 62.50 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.35 | 95.76 | 93.95 | 100.00 | 73.68 | 91.67 | 99.49 | 70.90 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 103 failures:
2.hmac_stress_all_with_rand_reset.90235115347192763016206312541161492020563008044098820527159308522867210578749
Line 8429, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21874330214 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 21874330214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.hmac_stress_all_with_rand_reset.37605227827887134897972109528327904858519131121405901884041039060567193593563
Line 8273, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12570097495 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12570097495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 101 more failures.
UVM_FATAL (hmac_smoke_vseq.sv:139) [hmac_error_vseq] wait timeout occurred! has 58 failures:
0.hmac_error.21105057706270210029079388641053943060825283759099267334841888811610166220478
Line 5546, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_error/latest/run.log
UVM_FATAL @ 10489963651 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 10489963651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.hmac_error.88523246741588513764066619506122636213256938579609889679692343059190469203658
Line 1159, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_error/latest/run.log
UVM_FATAL @ 10573830669 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 10573830669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
0.hmac_stress_all_with_rand_reset.27400401911214524171171181295594786071885675121931262827727438399531998746860
Line 396, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10063063999 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 10063063999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.hmac_stress_all_with_rand_reset.74729922532594669463975733602538493160749920306148260289416917047024706776104
Line 30902, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/15.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 186094008374 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 186094008374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
10.hmac_stress_all.36144183329497149254151699701118134863973873503250513107870745579759218401719
Line 1487, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_stress_all/latest/run.log
UVM_FATAL @ 11912358082 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 11912358082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.hmac_stress_all.88276998376077233320800713396389030414068294041250171908644499107773285235664
Line 272232, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_stress_all/latest/run.log
UVM_FATAL @ 314380507711 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 314380507711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (hmac_scoreboard.sv:346) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 35 failures:
3.hmac_wipe_secret.540449131765505624604632742007475251545631031879055158729213256990896601115
Line 4264, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 706674327 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3439777830 [0xcd06d826] vs 1814391771 [0x6c256bdb])
UVM_INFO @ 706674327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.hmac_wipe_secret.39758883120350481090599505229004563214962126200833518671583705507782321732621
Line 1581, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 1298003772 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3119263024 [0xb9ec2d30] vs 355665052 [0x1533049c])
UVM_INFO @ 1298003772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
5.hmac_stress_all.46494870621971188018260320416399703254043436526548047023076759016338686237604
Line 5477, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all/latest/run.log
UVM_ERROR @ 1124442293 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3600446910 [0xd69a75be] vs 2741543724 [0xa368a32c])
UVM_INFO @ 1124442293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.hmac_stress_all.29447572029756322305539560515778989955530729512216158640920185722212328422908
Line 26819, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_stress_all/latest/run.log
UVM_ERROR @ 8879310814 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (656239823 [0x271d6ccf] vs 1472393293 [0x57c2f04d])
UVM_INFO @ 8879310814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
16.hmac_stress_all_with_rand_reset.70844977358893375006307721995158364721514011169921683219856647128214958181566
Line 3573, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/16.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 655938026 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1583284839 [0x5e5f0267] vs 890731791 [0x35177d0f])
UVM_INFO @ 655938026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.hmac_stress_all_with_rand_reset.16650524661238884745652898870619172314156612685221020260283729093380389941415
Line 61612, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/18.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4613406621 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (368159362 [0x15f1aa82] vs 2635199524 [0x9d11f424])
UVM_INFO @ 4613406621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (hmac_scoreboard.sv:336) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 35 failures:
6.hmac_wipe_secret.10289421026323531535705637627541034872197484086757425445203816603672236705163
Line 1359, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 900642963 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1960009516 [0x74d35f2c] vs 2317685131 [0x8a25118b])
UVM_INFO @ 900642963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.hmac_wipe_secret.40014577003148087950495095774304925339084181873841613306753155804643468810771
Line 1128, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 318164405 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2517180011 [0x96091e6b] vs 1680710511 [0x642d9b6f])
UVM_INFO @ 318164405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
17.hmac_error.73268639693080968432420754428650453616071865763505625959141387561390849485891
Line 1447, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_error/latest/run.log
UVM_ERROR @ 891867837 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 2609818390 [0x9b8eab16])
UVM_INFO @ 891867837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.hmac_error.85374528355056567593863539525711955756755390917036334144533275926085672460621
Line 5909, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/42.hmac_error/latest/run.log
UVM_ERROR @ 722818915 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3992619874 [0xedfa8b62])
UVM_INFO @ 722818915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
17.hmac_stress_all.90251560293093316357327868151199568578485544453415339554055730061469239058242
Line 23617, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_stress_all/latest/run.log
UVM_ERROR @ 852026820 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2936377722 [0xaf05917a] vs 4018217159 [0xef8120c7])
UVM_INFO @ 852026820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.hmac_stress_all.71092519993982665650760380728623258255858404951833064376084840399781157246321
Line 18229, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/21.hmac_stress_all/latest/run.log
UVM_ERROR @ 31271120214 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3879021970 [0xe7352d92])
UVM_INFO @ 31271120214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
35.hmac_stress_all_with_rand_reset.69622178997012266933275034790757870716270018668853735174766855492650232125391
Line 11367, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/35.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19627811180 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1369335292 [0x519e65fc] vs 1585806946 [0x5e857e62])
UVM_INFO @ 19627811180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.hmac_stress_all_with_rand_reset.28463397943742236519874565398542172067443381837721623964499182399358763490157
Line 317786, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/46.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 115990602512 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2815663250 [0xa7d39c92] vs 100179776 [0x5f89f40])
UVM_INFO @ 115990602512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_ERROR (hmac_scoreboard.sv:349) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 32 failures:
2.hmac_stress_all.37030330750084781855349179166355598373486625505344905724757116283072832016664
Line 76783, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all/latest/run.log
UVM_ERROR @ 4447233105 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2181743704 [0x820ac458] vs 1359307905 [0x51056481])
UVM_INFO @ 4447233105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.hmac_stress_all.34356116237682234301889052461608927241109307779546657883506992224081231422738
Line 7175, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all/latest/run.log
UVM_ERROR @ 3392309128 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (4184477877 [0xf96a10b5] vs 357577031 [0x15503147])
UVM_INFO @ 3392309128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
10.hmac_wipe_secret.82361354070764315397673942158167212957586640919637618283482376087301058142997
Line 4697, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 15736398229 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (377726128 [0x1683a4b0] vs 2342002544 [0x8b981f70])
UVM_INFO @ 15736398229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.hmac_wipe_secret.62849083711980907402395617007493159937856176268200399736031135357546916130059
Line 619, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 66203014 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1938367061 [0x73892255] vs 2501441197 [0x9518f6ad])
UVM_INFO @ 66203014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
11.hmac_stress_all_with_rand_reset.49396445554736847641277270365910035613139598922137026152834493989824056482161
Line 59041, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4202338036 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2262467644 [0x86da843c] vs 3921306272 [0xe9ba62a0])
UVM_INFO @ 4202338036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.hmac_stress_all_with_rand_reset.61549656342873142312319293223586044265529595185876961772260114003457967221585
Line 1859, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 893856069 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2794866561 [0xa6964781] vs 4282176241 [0xff3cd2f1])
UVM_INFO @ 893856069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
36.hmac_error.88929086328596619882280684568303154245303192428795484831536339223014755293802
Line 6226, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/36.hmac_error/latest/run.log
UVM_ERROR @ 649813901 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 2750140965 [0xa3ebd225])
UVM_INFO @ 649813901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_scoreboard.sv:333) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 30 failures:
0.hmac_wipe_secret.76210517495097447963044614993425869738009763792637469847139714888501354765710
Line 917, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 707439374 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1076171226 [0x402511da] vs 3687422684 [0xdbc99adc])
UVM_INFO @ 707439374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_wipe_secret.101876697093220053634235638229885279286289034843812885433750680966181651356979
Line 6041, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 6411111485 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2825760139 [0xa86dad8b] vs 1206835581 [0x47eed97d])
UVM_INFO @ 6411111485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
1.hmac_stress_all_with_rand_reset.98410687349590285364550820085956040968639579922316891042256105761794400748956
Line 3502, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6752739146 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (428134376 [0x1984cfe8] vs 1439344707 [0x55caa843])
UVM_INFO @ 6752739146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.hmac_stress_all_with_rand_reset.47816052509503134044803923712000471525370357669224340685057226166682296448353
Line 1241, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 669898494 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3718561127 [0xdda4bd67] vs 3183013758 [0xbdb8ef7e])
UVM_INFO @ 669898494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
3.hmac_stress_all.66136356875356690787135223014301613020786167548927973043480339946572723360036
Line 1329, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all/latest/run.log
UVM_ERROR @ 254215848 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2816514736 [0xa7e09ab0] vs 1105033936 [0x41dd7ad0])
UVM_INFO @ 254215848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.hmac_stress_all.104398930142181237705292913880633581694318139559338035923263256743399114721943
Line 17415, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_stress_all/latest/run.log
UVM_ERROR @ 13175081100 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3561919823 [0xd44e954f] vs 3206745791 [0xbf230ebf])
UVM_INFO @ 13175081100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=*) == * has 14 failures:
Test hmac_error has 9 failures.
1.hmac_error.102819915987443669335954692916698837393765650660018527451926187396494929165654
Line 6703, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_error/latest/run.log
UVM_FATAL @ 11756561806 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x9080c000) == 0x1
UVM_INFO @ 11756561806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.hmac_error.4066835286598798815582764067555925666474351658543141931342179068579075492254
Line 9497, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_error/latest/run.log
UVM_FATAL @ 20876037379 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xaee48000) == 0x1
UVM_INFO @ 20876037379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Test hmac_stress_all has 2 failures.
9.hmac_stress_all.80818322920349089434332081509425949366260946530457218184352142518562341698400
Line 90504, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all/latest/run.log
UVM_FATAL @ 42577218005 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x23944000) == 0x1
UVM_INFO @ 42577218005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.hmac_stress_all.52249543776487746564745425337682050338157314217761636031451485325497040790806
Line 24759, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/36.hmac_stress_all/latest/run.log
UVM_FATAL @ 27763872470 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x5c4e2000) == 0x1
UVM_INFO @ 27763872470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 3 failures.
38.hmac_stress_all_with_rand_reset.40779309223869063421736373123275931380342053864518086819183885387108930800994
Line 5203, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/38.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 13012937832 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x828c8000) == 0x1
UVM_INFO @ 13012937832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
69.hmac_stress_all_with_rand_reset.19395906834249449555362778500165210699181103325188911015375239719337852668841
Line 3028, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/69.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10251964053 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x6afba000) == 0x1
UVM_INFO @ 10251964053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (hmac_scoreboard.sv:324) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 7 failures:
12.hmac_stress_all_with_rand_reset.50195274301545273569124806757849970041928161048419360221906294930685493574897
Line 36325, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/12.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 41091742460 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3581304893 [0xd576603d])
UVM_INFO @ 41091742460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
87.hmac_stress_all_with_rand_reset.6157804917079182035095578299607222680757102295692583231452004518283710698585
Line 16000, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/87.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15637604360 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 4194053687 [0xf9fc2e37])
UVM_INFO @ 15637604360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
13.hmac_error.59845844901891647508449011540359525526679497092685661302268908012834284666297
Line 10011, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_error/latest/run.log
UVM_ERROR @ 4958870764 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3157178290 [0xbc2eb7b2])
UVM_INFO @ 4958870764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.hmac_error.86985734752217948093505165789088721396746170878948361068960954176824558478278
Line 7687, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/31.hmac_error/latest/run.log
UVM_ERROR @ 2972754047 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 1455966343 [0x56c84887])
UVM_INFO @ 2972754047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (hmac_scoreboard.sv:312) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 5 failures:
7.hmac_stress_all_with_rand_reset.58869803921119461017261874461833334531016010485104974362583048164821853596465
Line 23317, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2069835748 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 2069835748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
159.hmac_stress_all_with_rand_reset.75788835971233408941552967610189380207519901275139574192769897113679318658367
Line 13564, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/159.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11124665022 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 11124665022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (hmac_scoreboard.sv:635) [scoreboard] Check failed cfg.hmac_vif.is_idle() == val (* [*] vs * [*]) has 1 failures:
2.hmac_error.3932286898380926278088638837671003485056926586384407543939090912596521386091
Line 8098, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_error/latest/run.log
UVM_ERROR @ 826840855 ps: (hmac_scoreboard.sv:635) [uvm_test_top.env.scoreboard] Check failed cfg.hmac_vif.is_idle() == val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 826840855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---