00fe426038| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.120s | 899.575us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.000s | 20.874us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 1.010s | 137.278us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 17.450s | 1.593ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 9.180s | 1.701ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 16.546m | 242.366ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 1.010s | 137.278us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 9.180s | 1.701ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.072m | 25.668ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.128m | 5.443ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.123m | 176.737ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.410s | 287.512us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.251m | 5.710ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 21.675m | 8.076ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 7.074m | 10.506ms | 9 | 50 | 18.00 |
| V2 | wipe_secret | hmac_wipe_secret | 32.770s | 2.389ms | 4 | 50 | 8.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 1.153h | 164.340ms | 13 | 50 | 26.00 |
| V2 | alert_test | hmac_alert_test | 0.660s | 15.875us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.700s | 18.436us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.550s | 775.218us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.550s | 775.218us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.000s | 20.874us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.010s | 137.278us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 9.180s | 1.701ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.480s | 117.966us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.000s | 20.874us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.010s | 137.278us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 9.180s | 1.701ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.480s | 117.966us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 466 | 590 | 78.98 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.050s | 96.685us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.680s | 230.384us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.680s | 230.384us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.120s | 899.575us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.184h | 192.331ms | 1 | 200 | 0.50 |
| V3 | TOTAL | 1 | 200 | 0.50 | |||
| TOTAL | 597 | 920 | 64.89 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 10 | 62.50 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.86 | 95.76 | 94.06 | 100.00 | 63.16 | 91.67 | 99.49 | 70.90 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 131 failures:
0.hmac_stress_all_with_rand_reset.109677568657967434544378361592927559213595739367580255013925584281797207881797
Line 34482, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5938130376 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5938130376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.hmac_stress_all_with_rand_reset.46272836362165927958589594556091104660421730419024462662755599544510581448031
Line 829, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 106443145 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 106443145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 129 more failures.
UVM_FATAL (hmac_smoke_vseq.sv:139) [hmac_error_vseq] wait timeout occurred! has 48 failures:
0.hmac_stress_all.108825385158371107312091343423501709248328022784317580915117429392660169072727
Line 3892, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest/run.log
UVM_FATAL @ 39080268608 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 39080268608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.hmac_stress_all.36058141591692446963284506162136037590705487672500421015742275979754963693258
Line 11874, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all/latest/run.log
UVM_FATAL @ 17844882486 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 17844882486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
1.hmac_error.99379521819706239117180826538707608585016336716798077187351009962849068271988
Line 17343, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_error/latest/run.log
UVM_FATAL @ 107067216075 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 107067216075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.hmac_error.62365382570302934584326342291265728706825950458891515847174905469504590925378
Line 7968, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_error/latest/run.log
UVM_FATAL @ 12864189208 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 12864189208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
9.hmac_stress_all_with_rand_reset.32100748740332383285946684790721307608928085119712496611503131883378411522085
Line 11596, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 27689502766 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 27689502766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.hmac_stress_all_with_rand_reset.97828383643039535359291259586264687529537645809788035398154436352843325260203
Line 287, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/28.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10170900920 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 10170900920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (hmac_scoreboard.sv:349) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 36 failures:
Test hmac_wipe_secret has 13 failures.
1.hmac_wipe_secret.1214583442529574589444005666911804290892783292255229224475009734853349338963
Line 2955, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 1144102330 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (3839436322 [0xe4d92622] vs 3895938038 [0xe8374bf6])
UVM_INFO @ 1144102330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.hmac_wipe_secret.86525804291489806221397549866083177735770139995290640216384798387008806291419
Line 1719, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 537699677 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (84316898 [0x50692e2] vs 969366611 [0x39c75c53])
UVM_INFO @ 537699677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Test hmac_stress_all has 5 failures.
2.hmac_stress_all.34899895567649915667173428454533962153377170064143742032215021520839212605526
Line 217603, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all/latest/run.log
UVM_ERROR @ 73830861374 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1322249488 [0x4ecfed10] vs 3199132149 [0xbeaee1f5])
UVM_INFO @ 73830861374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.hmac_stress_all.18677984508944015098403421261773158658292853605729617822776410919327137996702
Line 180461, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_stress_all/latest/run.log
UVM_ERROR @ 308060833086 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 4071494114 [0xf2ae11e2])
UVM_INFO @ 308060833086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test hmac_error has 2 failures.
9.hmac_error.50482830275297301836152257447529432989918546654682224604294632361857840383556
Line 13880, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_error/latest/run.log
UVM_ERROR @ 27772249895 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3170166396 [0xbcf4e67c])
UVM_INFO @ 27772249895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.hmac_error.89311595383179251889723824790732746609543094565709166206847230595028708098316
Line 4120, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/49.hmac_error/latest/run.log
UVM_ERROR @ 296190964 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3159200398 [0xbc4d928e])
UVM_INFO @ 296190964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 16 failures.
15.hmac_stress_all_with_rand_reset.59495602063734618562430548051961610378643095248522211013530935070447687350329
Line 68701, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/15.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 129879246169 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (3302298584 [0xc4d513d8] vs 328499606 [0x13948196])
UVM_INFO @ 129879246169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.hmac_stress_all_with_rand_reset.112597954478460513326974057652111583303629482796567731214070873446073126837624
Line 3908, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1345022052 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (266375584 [0xfe091a0] vs 3144038229 [0xbb663755])
UVM_INFO @ 1345022052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (hmac_scoreboard.sv:336) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 29 failures:
Test hmac_wipe_secret has 13 failures.
0.hmac_wipe_secret.1442124456860684047297402840480960428818571607200194854102051184413510669419
Line 697, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 115176536 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1505475206 [0x59bbba86] vs 1489502185 [0x58c7ffe9])
UVM_INFO @ 115176536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.hmac_wipe_secret.86828134486347213763843841059356285276332593868447182506575858391015879616658
Line 3385, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 861670797 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (332529025 [0x13d1fd81] vs 1437896928 [0x55b490e0])
UVM_INFO @ 861670797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Test hmac_stress_all has 4 failures.
5.hmac_stress_all.63073554744581495301530353440902334074125967458716051309459366233617420918065
Line 15188, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all/latest/run.log
UVM_ERROR @ 4619247302 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3852034163 [0xe5996073])
UVM_INFO @ 4619247302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.hmac_stress_all.103057995256678799781834408805387010723645815214078301681799874023617187140701
Line 18228, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/43.hmac_stress_all/latest/run.log
UVM_ERROR @ 2238748789 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (3031013118 [0xb4a996fe] vs 1495169340 [0x591e793c])
UVM_INFO @ 2238748789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test hmac_error has 2 failures.
20.hmac_error.71153296802784800801248097150361716103472202642489141457438853135721163229383
Line 8568, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/20.hmac_error/latest/run.log
UVM_ERROR @ 4085669620 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 1533809213 [0x5b6c123d])
UVM_INFO @ 4085669620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.hmac_error.39994893065823671736620358007491525209435396106807742331812828272357557243987
Line 9461, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/38.hmac_error/latest/run.log
UVM_ERROR @ 9146183060 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 2018836762 [0x7855011a])
UVM_INFO @ 9146183060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 10 failures.
35.hmac_stress_all_with_rand_reset.88772622056484104397087356796715105525384757413372032289617980756249257065784
Line 5890, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/35.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25557593230 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (3329669354 [0xc676b8ea] vs 17934480 [0x111a890])
UVM_INFO @ 25557593230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
52.hmac_stress_all_with_rand_reset.53492809787786805787264982532301465863213557818433831961637392590397258299702
Line 4987, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/52.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1860577061 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (4239244750 [0xfcadbdce] vs 3169541082 [0xbceb5bda])
UVM_INFO @ 1860577061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (hmac_scoreboard.sv:346) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 28 failures:
3.hmac_stress_all.38999069362513676829331304247759383575652155153635657770298671783988256649204
Line 78653, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all/latest/run.log
UVM_ERROR @ 33621935400 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (60729930 [0x39eaa4a] vs 1716018912 [0x66485ee0])
UVM_INFO @ 33621935400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.hmac_stress_all.14734762979580008133636103729441986703104437194112986445805852980914259569380
Line 71803, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all/latest/run.log
UVM_ERROR @ 3943286894 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (4260288704 [0xfdeed8c0] vs 1244170939 [0x4a288abb])
UVM_INFO @ 3943286894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
4.hmac_stress_all_with_rand_reset.8300982830967643626381852803933785201220727774863497051570457790513035749681
Line 23062, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6940186307 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3388594188 [0xc9f9d80c] vs 3463165921 [0xce6bb7e1])
UVM_INFO @ 6940186307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.hmac_stress_all_with_rand_reset.51671695165724368718419249045480027388407406831421084800525248425572155995608
Line 23594, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 76527578282 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3498784085 [0xd08b3555] vs 594058163 [0x23689bb3])
UVM_INFO @ 76527578282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
6.hmac_wipe_secret.96147700777971787942873820678512055603989673608150932282591962792529431541702
Line 1870, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 94434933 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (125957059 [0x781f3c3] vs 2546114455 [0x97c29f97])
UVM_INFO @ 94434933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.hmac_wipe_secret.48783528491833312610922921036790669641122393070777464839423580679648408824929
Line 2380, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 766081599 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3494795604 [0xd04e5954] vs 38046206 [0x24489fe])
UVM_INFO @ 766081599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (hmac_scoreboard.sv:333) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 21 failures:
Test hmac_error has 2 failures.
4.hmac_error.16781696504148153124828442502072785913479326552628935379417076081396447367623
Line 1636, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_error/latest/run.log
UVM_ERROR @ 576801851 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 18720754 [0x11da7f2])
UVM_INFO @ 576801851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.hmac_error.94975558430390715527896130424776459123578190903040896120792166793150840384845
Line 12628, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_error/latest/run.log
UVM_ERROR @ 1482181398 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 2168045080 [0x8139be18])
UVM_INFO @ 1482181398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all has 3 failures.
10.hmac_stress_all.43880593001067753436805359211590891771231654178720510585978994187682174880496
Line 4469, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_stress_all/latest/run.log
UVM_ERROR @ 7946890196 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1201938840 [0x47a42198] vs 2098211966 [0x7d102c7e])
UVM_INFO @ 7946890196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.hmac_stress_all.72963543371198933544312550696799706798445056186600012212768733947484668586013
Line 2152, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/27.hmac_stress_all/latest/run.log
UVM_ERROR @ 1439861719 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (289395256 [0x113fd238] vs 404263213 [0x1818912d])
UVM_INFO @ 1439861719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test hmac_wipe_secret has 9 failures.
11.hmac_wipe_secret.52728706667397015666056691411509538734279766107359000567807812887110987172256
Line 547, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 404160954 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2414896369 [0x8ff064f1] vs 2047260152 [0x7a06b5f8])
UVM_INFO @ 404160954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.hmac_wipe_secret.54670383063671472020727965688916326159842335441582505581801782536029537289631
Line 513, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 165841015 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1538795430 [0x5bb827a6] vs 3226258052 [0xc04cca84])
UVM_INFO @ 165841015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Test hmac_stress_all_with_rand_reset has 7 failures.
18.hmac_stress_all_with_rand_reset.61696255523520169060244820480586259121197785181605375660249189704443247284464
Line 34497, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/18.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 23963088867 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3874052741 [0xe6e95a85] vs 1835629546 [0x6d697bea])
UVM_INFO @ 23963088867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.hmac_stress_all_with_rand_reset.110286744932672407914454329522264394781089042976925097091712105002235555075577
Line 16506, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/23.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3432089508 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2161954417 [0x80dcce71] vs 4110113676 [0xf4fb5b8c])
UVM_INFO @ 3432089508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=*) == * has 15 failures:
0.hmac_error.32197643414378263818635481692238017230547400246517660415263766947328492972661
Line 1221, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_error/latest/run.log
UVM_FATAL @ 10356120510 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xa47d4000) == 0x1
UVM_INFO @ 10356120510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.hmac_error.37159183667701461198571218991710147280261923376395875004271475219472862636349
Line 13627, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_error/latest/run.log
UVM_FATAL @ 34891058665 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x74f68000) == 0x1
UVM_INFO @ 34891058665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
14.hmac_stress_all.46709909995195198058064640175409038667079264972715475554733313427304232949092
Line 15645, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_stress_all/latest/run.log
UVM_FATAL @ 27641109465 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x345de000) == 0x1
UVM_INFO @ 27641109465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.hmac_stress_all.96602011677033171107317700189432405424408061715003291420683404709931710661456
Line 36194, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/24.hmac_stress_all/latest/run.log
UVM_FATAL @ 17864179583 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x6b97a000) == 0x1
UVM_INFO @ 17864179583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
81.hmac_stress_all_with_rand_reset.24045084008529081523030442509356064021450839760142516488329466676378018256933
Line 38683, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/81.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 23482699913 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xb84da000) == 0x1
UVM_INFO @ 23482699913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
92.hmac_stress_all_with_rand_reset.25741388615883452333528755440490440274005123272663703639006314139443282505011
Line 593, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/92.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10060904693 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xd8bf2000) == 0x1
UVM_INFO @ 10060904693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (hmac_scoreboard.sv:312) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 8 failures:
1.hmac_stress_all_with_rand_reset.39987292421323380814871711086469947974753300347544641012073820862893222696764
Line 1094, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2742091729 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 2742091729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
108.hmac_stress_all_with_rand_reset.81026575093703657821306561696978902801515572001297157383115870737193889052147
Line 5474, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/108.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11784015352 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 11784015352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
8.hmac_stress_all.68176764624722162546701337358094718045290728806948902902972050033993095276456
Line 1368, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all/latest/run.log
UVM_ERROR @ 198488924 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 198488924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.hmac_stress_all.8451551606432179697188732917005245014252149151485216207180723034713058588720
Line 81598, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/22.hmac_stress_all/latest/run.log
UVM_ERROR @ 178201068017 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 178201068017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (hmac_scoreboard.sv:324) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 5 failures:
Test hmac_stress_all has 1 failures.
16.hmac_stress_all.8982241800088769471905545030805047021996240795602218096956770260850572239830
Line 88442, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/16.hmac_stress_all/latest/run.log
UVM_ERROR @ 9937754484 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 2240970518 [0x85927f16])
UVM_INFO @ 9937754484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_error has 2 failures.
26.hmac_error.83549642833529787373339291429107449049654408419404378420166784151569445486928
Line 8575, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/26.hmac_error/latest/run.log
UVM_ERROR @ 2465890027 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3202839892 [0xbee77554])
UVM_INFO @ 2465890027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.hmac_error.30284665510015311193685401736041489762233814461040248785102582380587742056572
Line 1670, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/32.hmac_error/latest/run.log
UVM_ERROR @ 375581050 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 2379721772 [0x8dd7ac2c])
UVM_INFO @ 375581050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 2 failures.
33.hmac_stress_all_with_rand_reset.29998356642807500601225968525249495721685196628911480141336862339113829286793
Line 7626, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/33.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2731231339 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 2714559005 [0xa1cce21d])
UVM_INFO @ 2731231339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
171.hmac_stress_all_with_rand_reset.3423150459056535622003518385858714630238403037119302919149782444242297533462
Line 15349, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/171.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5076131225 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 4161267683 [0xf807e7e3])
UVM_INFO @ 5076131225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_scoreboard.sv:635) [scoreboard] Check failed cfg.hmac_vif.is_idle() == val (* [*] vs * [*]) has 2 failures:
Test hmac_stress_all has 1 failures.
25.hmac_stress_all.71999738648575629215509594959183055202909655337556943475306757797559031759759
Line 12616, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/25.hmac_stress_all/latest/run.log
UVM_ERROR @ 2784085764 ps: (hmac_scoreboard.sv:635) [uvm_test_top.env.scoreboard] Check failed cfg.hmac_vif.is_idle() == val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2784085764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_error has 1 failures.
39.hmac_error.74355575285952460124159315144385398521777115517713946452151175729220023702990
Line 8803, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/39.hmac_error/latest/run.log
UVM_ERROR @ 4347846912 ps: (hmac_scoreboard.sv:635) [uvm_test_top.env.scoreboard] Check failed cfg.hmac_vif.is_idle() == val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4347846912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---