HMAC Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.860s 693.003us 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.040s 405.642us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.990s 35.349us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 16.540s 2.338ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 8.530s 622.477us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 13.465m 82.643ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.990s 35.349us 20 20 100.00
hmac_csr_aliasing 8.530s 622.477us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 2.274m 7.015ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.205m 5.567ms 50 50 100.00
V2 test_vectors hmac_test_sha_vectors 9.892m 535.542ms 50 50 100.00
hmac_test_hmac_vectors 1.540s 395.445us 50 50 100.00
V2 burst_wr hmac_burst_wr 1.050m 4.620ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 24.807m 75.196ms 50 50 100.00
V2 error hmac_error 7.384m 10.091ms 7 50 14.00
V2 wipe_secret hmac_wipe_secret 25.190s 1.673ms 7 50 14.00
V2 save_and_restore save_and_restore 0 0 --
V2 fifo_empty_status_interrupt fifo_empty_status_interrupt 0 0 --
V2 wide_digest_configurable_key_length wide_digest_configurable_key_length 0 0 --
V2 stress_all hmac_stress_all 55.254m 209.092ms 16 50 32.00
V2 alert_test hmac_alert_test 0.650s 16.767us 50 50 100.00
V2 intr_test hmac_intr_test 0.680s 48.333us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.530s 825.441us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.530s 825.441us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.040s 405.642us 5 5 100.00
hmac_csr_rw 0.990s 35.349us 20 20 100.00
hmac_csr_aliasing 8.530s 622.477us 5 5 100.00
hmac_same_csr_outstanding 2.540s 563.631us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.040s 405.642us 5 5 100.00
hmac_csr_rw 0.990s 35.349us 20 20 100.00
hmac_csr_aliasing 8.530s 622.477us 5 5 100.00
hmac_same_csr_outstanding 2.540s 563.631us 20 20 100.00
V2 TOTAL 470 590 79.66
V2S tl_intg_err hmac_sec_cm 1.000s 895.472us 5 5 100.00
hmac_tl_intg_err 4.480s 1.075ms 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.480s 1.075ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.860s 693.003us 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.194h 94.282ms 4 200 2.00
V3 TOTAL 4 200 2.00
TOTAL 604 920 65.65

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 13 10 62.50
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
89.41 95.76 94.06 100.00 73.68 91.67 99.49 71.18

Failure Buckets

Past Results