349bab6601| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.860s | 693.003us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.040s | 405.642us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.990s | 35.349us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 16.540s | 2.338ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.530s | 622.477us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 13.465m | 82.643ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.990s | 35.349us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.530s | 622.477us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.274m | 7.015ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.205m | 5.567ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.892m | 535.542ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.540s | 395.445us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.050m | 4.620ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 24.807m | 75.196ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 7.384m | 10.091ms | 7 | 50 | 14.00 |
| V2 | wipe_secret | hmac_wipe_secret | 25.190s | 1.673ms | 7 | 50 | 14.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 55.254m | 209.092ms | 16 | 50 | 32.00 |
| V2 | alert_test | hmac_alert_test | 0.650s | 16.767us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.680s | 48.333us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.530s | 825.441us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.530s | 825.441us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.040s | 405.642us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.990s | 35.349us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.530s | 622.477us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.540s | 563.631us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.040s | 405.642us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.990s | 35.349us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.530s | 622.477us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.540s | 563.631us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 470 | 590 | 79.66 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.000s | 895.472us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.480s | 1.075ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.480s | 1.075ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.860s | 693.003us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.194h | 94.282ms | 4 | 200 | 2.00 |
| V3 | TOTAL | 4 | 200 | 2.00 | |||
| TOTAL | 604 | 920 | 65.65 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 10 | 62.50 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.41 | 95.76 | 94.06 | 100.00 | 73.68 | 91.67 | 99.49 | 71.18 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 106 failures:
0.hmac_stress_all_with_rand_reset.24512810441450593560211592131530118228647289745775934502421550071531695533257
Line 17876, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10487521952 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10487521952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.100204980122492860016151358931249245435347326543564173925525799464237066325542
Line 69149, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9196257786 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9196257786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 104 more failures.
UVM_FATAL (hmac_smoke_vseq.sv:139) [hmac_error_vseq] wait timeout occurred! has 59 failures:
0.hmac_error.22171902304839323922239179120545989655791800594894421736954700090931617042099
Line 3018, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_error/latest/run.log
UVM_FATAL @ 10981755316 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 10981755316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_error.32930685099680046043829663862646918607570129366703470635404460282775645557441
Line 2523, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_error/latest/run.log
UVM_FATAL @ 10180049517 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 10180049517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
4.hmac_stress_all.63886832183881993708152225785116408019436864292145549431025464435480394869156
Line 6584, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all/latest/run.log
UVM_FATAL @ 13742625817 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 13742625817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.hmac_stress_all.32985571529661818798905103028936391419468988787183994419773026915099210144057
Line 98321, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all/latest/run.log
UVM_FATAL @ 155856560224 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 155856560224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
5.hmac_stress_all_with_rand_reset.12274901382716928334150711194815340813007410140648245308818232680673862752944
Line 2632, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 16794495144 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 16794495144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.hmac_stress_all_with_rand_reset.109979691725047536118863122312245627419979386435378114724232232484983099179971
Line 6418, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 23486326712 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 23486326712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (hmac_scoreboard.sv:349) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 37 failures:
0.hmac_wipe_secret.83040419163336837874101104959641819434539404519543215401968405445808886359611
Line 2345, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 393619167 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (170376357 [0xa27bca5] vs 1985912602 [0x765e9f1a])
UVM_INFO @ 393619167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_wipe_secret.38614395459644977059924593078240821098214873354013114556599269096563552376655
Line 1300, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 191383197 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1840639731 [0x6db5eef3] vs 2731411204 [0xa2ce0704])
UVM_INFO @ 191383197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
6.hmac_stress_all.40619779282233595222135402203897002470209825898024189914981432528957763575698
Line 87123, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all/latest/run.log
UVM_ERROR @ 60168666123 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (736554331 [0x2be6ed5b] vs 1789786196 [0x6aadf854])
UVM_INFO @ 60168666123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.hmac_stress_all.79344418856203396907666376328641477447172480715139171853242698409114234672700
Line 196644, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/36.hmac_stress_all/latest/run.log
UVM_ERROR @ 1155710033537 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (4077436393 [0xf308bde9] vs 2808131640 [0xa760b038])
UVM_INFO @ 1155710033537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
22.hmac_stress_all_with_rand_reset.58931262108517864271680738723815373496763443714638379594367393523610134788591
Line 11654, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/22.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5067353938 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1045307188 [0x3e4e1f34] vs 1561118945 [0x5d0cc8e1])
UVM_INFO @ 5067353938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.hmac_stress_all_with_rand_reset.101787458337524320590830395264702043154025111767616152241265152451669798394133
Line 6222, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/33.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4769201358 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2294195826 [0x88bea672] vs 837646427 [0x31ed785b])
UVM_INFO @ 4769201358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
43.hmac_error.52139077023603635589206539183060663169682596839725695834488457912289623253361
Line 12951, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/43.hmac_error/latest/run.log
UVM_ERROR @ 5306448076 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3089579107 [0xb8273c63])
UVM_INFO @ 5306448076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_scoreboard.sv:333) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 29 failures:
7.hmac_wipe_secret.3918360456175050139075158080564184718256298724223591986313690330245433561167
Line 2480, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 448192242 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3314337669 [0xc58cc785] vs 2138181830 [0x7f7210c6])
UVM_INFO @ 448192242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.hmac_wipe_secret.63104652713460282835607093740377840735059410136905261660626298985161978738530
Line 2580, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 509369088 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1643151904 [0x61f08220] vs 277179335 [0x10856bc7])
UVM_INFO @ 509369088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
8.hmac_stress_all.61609483530509882863883421877966909000250359434808184660094416860395548597425
Line 126890, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all/latest/run.log
UVM_ERROR @ 140466912195 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1844758979 [0x6df4c9c3] vs 2641705910 [0x9d753bb6])
UVM_INFO @ 140466912195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.hmac_stress_all.15433437967922111801094322796756805071033530186371342992341900958005957845527
Line 170085, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_stress_all/latest/run.log
UVM_ERROR @ 293519745176 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2702390594 [0xa1133542] vs 4250936802 [0xfd6025e2])
UVM_INFO @ 293519745176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
19.hmac_stress_all_with_rand_reset.4418371714723646048157591519625545460915949215175554615919045976876645810736
Line 33716, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/19.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9000316500 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1020448094 [0x3cd2cd5e] vs 2053780202 [0x7a6a32ea])
UVM_INFO @ 9000316500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.hmac_stress_all_with_rand_reset.51970741171457274222340740856638035830440780265132806277589377553739690848366
Line 19055, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/21.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27145408774 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (936014505 [0x37ca72a9] vs 3183013758 [0xbdb8ef7e])
UVM_INFO @ 27145408774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (hmac_scoreboard.sv:336) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 28 failures:
2.hmac_wipe_secret.14867620353293789903349505370773792278524603476478463254960797372025857838787
Line 1232, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 178035119 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (3011306148 [0xb37ce2a4] vs 2874573135 [0xab56814f])
UVM_INFO @ 178035119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.hmac_wipe_secret.73820859973824307426399290840783562629759231802081755668984215591963523697066
Line 1617, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 756771769 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2321838763 [0x8a6472ab] vs 1417556904 [0x547e33a8])
UVM_INFO @ 756771769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
9.hmac_stress_all_with_rand_reset.14821819707127137219119428186401105106211037818489368852727713781890448989353
Line 2076, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2428261534 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2980677610 [0xb1a987ea] vs 3460955890 [0xce49fef2])
UVM_INFO @ 2428261534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.hmac_stress_all_with_rand_reset.624682442549130488357854602475131267321581446853101532289527339320550568942
Line 1129, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/15.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 70683118 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (666875545 [0x27bfb699] vs 4228345792 [0xfc076fc0])
UVM_INFO @ 70683118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
20.hmac_stress_all.33230098619372287050790331859492986329553049441717576896516332919895749313676
Line 235059, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/20.hmac_stress_all/latest/run.log
UVM_ERROR @ 20783441940 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (3469205503 [0xcec7dfff] vs 4277764147 [0xfef98033])
UVM_INFO @ 20783441940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.hmac_stress_all.1257102066946600723035931915597249132561835257899179871930601057321498994089
Line 109519, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/49.hmac_stress_all/latest/run.log
UVM_ERROR @ 16959597059 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (907880120 [0x361d26b8] vs 903971791 [0x35e183cf])
UVM_INFO @ 16959597059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_scoreboard.sv:346) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 27 failures:
13.hmac_wipe_secret.26551378847721575522837317258543171836624681275912965659007927477325901584782
Line 1028, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 1713871717 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2382121668 [0x8dfc4ac4] vs 1432618892 [0x5564078c])
UVM_INFO @ 1713871717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.hmac_wipe_secret.20566819663639926163876830972394966173900433162632660960836975265123936760847
Line 2365, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/26.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 706847454 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2313496321 [0x89e52701] vs 836414277 [0x31daab45])
UVM_INFO @ 706847454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
24.hmac_stress_all.67056355325131084671270672305923752898375987682869381810399542165301728428187
Line 48168, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/24.hmac_stress_all/latest/run.log
UVM_ERROR @ 32685419162 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 668348894 [0x27d631de])
UVM_INFO @ 32685419162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.hmac_stress_all.77068293291176869632127615488113095531675275151911975116824240902437961352077
Line 64540, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/33.hmac_stress_all/latest/run.log
UVM_ERROR @ 41891166012 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3129645646 [0xba8a9a4e] vs 875382858 [0x342d484a])
UVM_INFO @ 41891166012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
25.hmac_stress_all_with_rand_reset.33454885860347409349275667571336037227116642750868431914494002593432827287364
Line 988, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/25.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 373748010 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (4249230381 [0xfd461c2d] vs 1378142584 [0x5224c978])
UVM_INFO @ 373748010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.hmac_stress_all_with_rand_reset.29276731408611306872291197416309289473248359819039038036406846502646590337348
Line 2104, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/29.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 163307157 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3041082777 [0xb5433d99] vs 3268487880 [0xc2d12ac8])
UVM_INFO @ 163307157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
46.hmac_error.4344549971386534310239634466138157578194792792742818025089220572073239851478
Line 3441, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/46.hmac_error/latest/run.log
UVM_ERROR @ 638318529 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 505196320 [0x1e1caf20])
UVM_INFO @ 638318529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=*) == * has 15 failures:
Test hmac_stress_all has 1 failures.
0.hmac_stress_all.66403422416172682705923840690176483371488641701465252709905492320864876371908
Line 3756, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest/run.log
UVM_FATAL @ 10872407034 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x911e8000) == 0x1
UVM_INFO @ 10872407034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_error has 10 failures.
8.hmac_error.13929219279533244063469416526431445752411613189640274042196125568637038851158
Line 15557, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_error/latest/run.log
UVM_FATAL @ 134268186758 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x8c2c2000) == 0x1
UVM_INFO @ 134268186758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.hmac_error.52176629718063716717642169602122992785744750258606620444759035122496760200944
Line 263, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_error/latest/run.log
UVM_FATAL @ 10006734325 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x1f900000) == 0x1
UVM_INFO @ 10006734325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Test hmac_stress_all_with_rand_reset has 4 failures.
41.hmac_stress_all_with_rand_reset.20371059044275213340223967033998161832083727524477451471420302588304885651441
Line 92261, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/41.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 64033914165 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x4ea5c000) == 0x1
UVM_INFO @ 64033914165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
69.hmac_stress_all_with_rand_reset.114628538250161318623093905899671712089137040356877781085984915623798650441524
Line 976, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/69.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11626438924 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xf807e000) == 0x1
UVM_INFO @ 11626438924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (hmac_scoreboard.sv:312) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 9 failures:
Test hmac_stress_all has 2 failures.
5.hmac_stress_all.16658541762454521857775580006090397270182002711576122361659716691124152021070
Line 96788, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all/latest/run.log
UVM_ERROR @ 67716920017 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 67716920017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.hmac_stress_all.31032654537597248099905863964080244297693846242857290481007444200304113743214
Line 14219, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/25.hmac_stress_all/latest/run.log
UVM_ERROR @ 6453443762 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 6453443762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 7 failures.
72.hmac_stress_all_with_rand_reset.89434249221070181088319493783956184233673256418969811182369842409258843668214
Line 57571, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/72.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15312639269 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 15312639269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
77.hmac_stress_all_with_rand_reset.112980559632566737898146893569494054554907820089610840662652301151757967945489
Line 5123, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/77.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18501393203 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 18501393203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (hmac_scoreboard.sv:324) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 5 failures:
Test hmac_error has 1 failures.
14.hmac_error.76778218040673038069363703477572649363151374522870381459734620611556479828970
Line 42576, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_error/latest/run.log
UVM_ERROR @ 54472333001 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3009094835 [0xb35b24b3])
UVM_INFO @ 54472333001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all has 2 failures.
14.hmac_stress_all.73482413365725338970564141759867881536240995253600513254393442556710768815047
Line 4301, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_stress_all/latest/run.log
UVM_ERROR @ 4523735665 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 1532365692 [0x5b560b7c])
UVM_INFO @ 4523735665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.hmac_stress_all.110588038944977670284606183498461843756563572375278051253397331336093454925787
Line 65638, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/19.hmac_stress_all/latest/run.log
UVM_ERROR @ 4695148074 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 1054548523 [0x3edb222b])
UVM_INFO @ 4695148074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 2 failures.
107.hmac_stress_all_with_rand_reset.9480091593814538549316882389260967325361656493384668059045312192537512990637
Line 10779, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/107.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6085975721 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 390339892 [0x17441d34])
UVM_INFO @ 6085975721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
139.hmac_stress_all_with_rand_reset.28037789907972424234186818239323388981822006170222088465637895064988308890488
Line 19812, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/139.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2962814364 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 1071254340 [0x3fda0b44])
UVM_INFO @ 2962814364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_scoreboard.sv:635) [scoreboard] Check failed cfg.hmac_vif.is_idle() == val (* [*] vs * [*]) has 1 failures:
44.hmac_error.109370931962066399904315293501429799679498617965271207387334411138570689349352
Line 15935, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/44.hmac_error/latest/run.log
UVM_ERROR @ 31562981599 ps: (hmac_scoreboard.sv:635) [uvm_test_top.env.scoreboard] Check failed cfg.hmac_vif.is_idle() == val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 31562981599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---