eb776817a5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.850s | 686.773us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.030s | 164.394us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.950s | 112.955us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 9.870s | 836.488us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.140s | 159.127us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 12.620m | 390.705ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.950s | 112.955us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.140s | 159.127us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.336m | 6.931ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.157m | 1.552ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.719m | 43.965ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.490s | 277.989us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.133m | 2.684ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 21.573m | 8.304ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 6.878m | 10.146ms | 19 | 50 | 38.00 |
| V2 | wipe_secret | hmac_wipe_secret | 21.350s | 1.135ms | 7 | 50 | 14.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 38.452m | 64.258ms | 6 | 50 | 12.00 |
| V2 | alert_test | hmac_alert_test | 0.660s | 42.802us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.710s | 32.430us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.780s | 1.584ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.780s | 1.584ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.030s | 164.394us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.950s | 112.955us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.140s | 159.127us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.620s | 302.516us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.030s | 164.394us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.950s | 112.955us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.140s | 159.127us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.620s | 302.516us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 472 | 590 | 80.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.920s | 58.036us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.680s | 284.258us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.680s | 284.258us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.850s | 686.773us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.024h | 45.033ms | 0 | 200 | 0.00 |
| V3 | TOTAL | 0 | 200 | 0.00 | |||
| TOTAL | 602 | 920 | 65.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 10 | 62.50 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.66 | 95.66 | 92.61 | 100.00 | 63.16 | 91.21 | 99.49 | 71.47 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 108 failures:
0.hmac_stress_all_with_rand_reset.14063464425219211586300626482627166560893846921350932539604035001770420263414
Line 3326, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 725217884 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 725217884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.hmac_stress_all_with_rand_reset.113407906841452280014046225428138459603560985958225142780077498389180299953806
Line 1743, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6707581035 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6707581035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 106 more failures.
UVM_FATAL (hmac_smoke_vseq.sv:139) [hmac_error_vseq] wait timeout occurred! has 50 failures:
0.hmac_error.24709547134091771874301555466168722858770798261716778096905172183289862412169
Line 5627, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_error/latest/run.log
UVM_FATAL @ 11543705921 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 11543705921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.hmac_error.105230972049060692579024488700894584719060285971802553087853320562899669218152
Line 6735, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_error/latest/run.log
UVM_FATAL @ 13109957889 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 13109957889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
1.hmac_stress_all.10830723060913573200106856050841794810383106999790191239331405720984374995137
Line 41960, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all/latest/run.log
UVM_FATAL @ 60420345926 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 60420345926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.hmac_stress_all.45872968721982911770618952089650075489497797802395608638933059845788465349147
Line 12122, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all/latest/run.log
UVM_FATAL @ 19069796140 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 19069796140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
3.hmac_stress_all_with_rand_reset.54350620991446157916162690493343358286497118669002739061523982012596310563920
Line 3892, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 16795900331 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 16795900331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.hmac_stress_all_with_rand_reset.111427151431930725646018251498005706281799199654940969640665715200271277366795
Line 132401, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/18.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 53599080326 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 53599080326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (hmac_scoreboard.sv:336) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 44 failures:
0.hmac_stress_all.99144918210863269720935093238264737432421073424640856653322899942633970917694
Line 80620, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest/run.log
UVM_ERROR @ 169491298828 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (3819547328 [0xe3a9aac0] vs 2327870098 [0x8ac07a92])
UVM_INFO @ 169491298828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.hmac_stress_all.27368169089782002241367884041278561263266865346812052550081918911582496268647
Line 142358, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_stress_all/latest/run.log
UVM_ERROR @ 250151471627 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (3976089293 [0xecfe4ecd] vs 498500836 [0x1db684e4])
UVM_INFO @ 250151471627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
1.hmac_stress_all_with_rand_reset.67178149331646493468056722004451600111672077522487950799870278903489226317786
Line 13070, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26967227610 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1763158413 [0x6917a98d] vs 1961260320 [0x74e67520])
UVM_INFO @ 26967227610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.hmac_stress_all_with_rand_reset.59789949699545514740854305429562013949481070503723881796238441319072395305936
Line 9068, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11274038524 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1125059785 [0x430f0cc9] vs 1180036967 [0x4655ef67])
UVM_INFO @ 11274038524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
2.hmac_wipe_secret.71548044182063898802738465808821442387445609807201124791664401657784878963288
Line 5506, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 1925884804 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1755850513 [0x68a82711] vs 2611695668 [0x9bab5034])
UVM_INFO @ 1925884804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.hmac_wipe_secret.3752947841362444019692184290932035536724317551798998030256193992862714314768
Line 5062, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 1105101741 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (4091042387 [0xf3d85a53] vs 3344530190 [0xc7597b0e])
UVM_INFO @ 1105101741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
16.hmac_error.81915563356285811754518456322420104337317198579331528763196184660374259957885
Line 22773, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/16.hmac_error/latest/run.log
UVM_ERROR @ 4293998095 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 1419146090 [0x5496736a])
UVM_INFO @ 4293998095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.hmac_error.93501884659787338321420603373079854060843769250627982437589759933476921682551
Line 9055, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_error/latest/run.log
UVM_ERROR @ 2832536061 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3369072289 [0xc8cff6a1])
UVM_INFO @ 2832536061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_scoreboard.sv:333) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 35 failures:
3.hmac_stress_all.73205212191354936048585782171050433567836802050422821489127993407625246177615
Line 2669, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all/latest/run.log
UVM_ERROR @ 320142287 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3954644185 [0xebb714d9] vs 1510793049 [0x5a0cdf59])
UVM_INFO @ 320142287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.hmac_stress_all.76163583068954480798555661423543941573186237375093817645522735874251826383615
Line 1049, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all/latest/run.log
UVM_ERROR @ 206288728 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1181065868 [0x4665a28c] vs 1506929026 [0x59d1e982])
UVM_INFO @ 206288728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
6.hmac_stress_all_with_rand_reset.79620539482446529116452405960014329606642775692553162034252811708671923035222
Line 5733, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1177977629 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2216108006 [0x84171fe6] vs 2633127721 [0x9cf25729])
UVM_INFO @ 1177977629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.hmac_stress_all_with_rand_reset.32837008652514823387788574414014393312763541193797700256615581997201717974276
Line 115902, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 37754824727 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 645454881 [0x2678dc21])
UVM_INFO @ 37754824727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
8.hmac_wipe_secret.3572740430386547527454750462825695792370067393847263760172644663202188663716
Line 2147, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 1978601597 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3064955314 [0xb6af81b2] vs 3183013758 [0xbdb8ef7e])
UVM_INFO @ 1978601597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.hmac_wipe_secret.28949083769534354018134950453307746852128042566101318266991704897732957200108
Line 1219, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/15.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 215910675 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (4062709916 [0xf228089c] vs 2158840563 [0x80ad4af3])
UVM_INFO @ 215910675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (hmac_scoreboard.sv:349) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 28 failures:
Test hmac_wipe_secret has 10 failures.
0.hmac_wipe_secret.49789280307297694191318179743686652671000958603434762454553518183348919119612
Line 808, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 35008044 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1137861412 [0x43d26324] vs 2526869240 [0x969cf6f8])
UVM_INFO @ 35008044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.hmac_wipe_secret.1741327840503665197230390676283405219649655894438974564233317632072954457693
Line 1610, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 498423047 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (961009734 [0x3947d846] vs 3553132186 [0xd3c87e9a])
UVM_INFO @ 498423047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Test hmac_stress_all_with_rand_reset has 16 failures.
12.hmac_stress_all_with_rand_reset.94840606740940459721196819479175060387191452246173096506304181072644618109127
Line 54447, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/12.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4096266542 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (4158914896 [0xf7e40150] vs 2682834117 [0x9fe8ccc5])
UVM_INFO @ 4096266542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.hmac_stress_all_with_rand_reset.52541897193076184608781290087292090837020392705676669311239111925379025649423
Line 941, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/16.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7481133326 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (3731607994 [0xde6bd1ba] vs 4170950027 [0xf89ba58b])
UVM_INFO @ 7481133326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
Test hmac_stress_all has 1 failures.
17.hmac_stress_all.27851820948841051058494325920865997138766138463970365895416496041574355867039
Line 348, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_stress_all/latest/run.log
UVM_ERROR @ 190991979 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (614255741 [0x249ccc7d] vs 1946721218 [0x74089bc2])
UVM_INFO @ 190991979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_error has 1 failures.
33.hmac_error.74518439327836444860376410266616555065122759204380936209700447873943221279206
Line 11002, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/33.hmac_error/latest/run.log
UVM_ERROR @ 5553883000 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 2251787516 [0x86378cfc])
UVM_INFO @ 5553883000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_scoreboard.sv:346) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 24 failures:
1.hmac_wipe_secret.37817267645804885640506716559321338834071171642595707846246662122537846696118
Line 1920, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 369901323 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (554923746 [0x211376e2] vs 3125347451 [0xba49047b])
UVM_INFO @ 369901323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.hmac_wipe_secret.81082018234776722351815915237220634541946775937894753453067166024852984071170
Line 2355, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 914645414 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (814249672 [0x308876c8] vs 1994810242 [0x76e66382])
UVM_INFO @ 914645414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
11.hmac_stress_all.107485368912358471914325229558996834394987351541859857706651484951425841028620
Line 5404, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_stress_all/latest/run.log
UVM_ERROR @ 2547063274 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 2743029808 [0xa37f5030])
UVM_INFO @ 2547063274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.hmac_stress_all.4187286517783291653892358732409371457885969181982153032401910749399052121549
Line 59872, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/16.hmac_stress_all/latest/run.log
UVM_ERROR @ 9005845887 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1788984218 [0x6aa1bb9a] vs 2931960817 [0xaec22bf1])
UVM_INFO @ 9005845887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
19.hmac_stress_all_with_rand_reset.31658857313965259651872258756120128964345002758165762420520970876850403691284
Line 3305, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/19.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16061373299 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (699375651 [0x29afa023] vs 2110139643 [0x7dc62cfb])
UVM_INFO @ 16061373299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.hmac_stress_all_with_rand_reset.62143517207344756269205618396990351254596005521209500572702961850709542642955
Line 32620, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/31.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2418381202 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1205876248 [0x47e03618] vs 949398609 [0x3896ac51])
UVM_INFO @ 2418381202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (hmac_scoreboard.sv:312) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 12 failures:
9.hmac_stress_all_with_rand_reset.95009776372095995272907390409676319160404793912796931699741768846585519407214
Line 2101, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 969843317 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 969843317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.hmac_stress_all_with_rand_reset.104414510514595513279884570911735026639331595160877360548243377922537090281003
Line 2423, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1782918230 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 1782918230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
13.hmac_stress_all.52983796098909384223838544939936666755268286574757048935054308500083788255577
Line 394, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_stress_all/latest/run.log
UVM_ERROR @ 314005789 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 314005789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.hmac_stress_all.103782553025982825508316030581976044298181300889411198306353844383915415631133
Line 81230, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/18.hmac_stress_all/latest/run.log
UVM_ERROR @ 31518692753 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 31518692753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=*) == * has 10 failures:
1.hmac_error.110090162098213987602457655148603319319747798086865438890723211030318320661645
Line 1818, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_error/latest/run.log
UVM_FATAL @ 10146405863 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x636e6000) == 0x1
UVM_INFO @ 10146405863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.hmac_error.89119801078217313671501103182931233519783583608390198178785051649259009997260
Line 358, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_error/latest/run.log
UVM_FATAL @ 10017124317 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x52bb8000) == 0x1
UVM_INFO @ 10017124317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
31.hmac_stress_all.25955731319292539933100412744546154438867114706605816379681591747750882617208
Line 330168, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/31.hmac_stress_all/latest/run.log
UVM_FATAL @ 120765438801 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x6ba02000) == 0x1
UVM_INFO @ 120765438801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.hmac_stress_all.49445592935166178504099273631347610901747628848290916504408231223453960674658
Line 169073, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/34.hmac_stress_all/latest/run.log
UVM_FATAL @ 22313767138 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xca892000) == 0x1
UVM_INFO @ 22313767138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (hmac_scoreboard.sv:324) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 6 failures:
Test hmac_stress_all has 1 failures.
44.hmac_stress_all.8770758482516613836885248279028513910495650151457674109441679441341471756236
Line 124613, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/44.hmac_stress_all/latest/run.log
UVM_ERROR @ 31443452311 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 352176894 [0x14fdcafe])
UVM_INFO @ 31443452311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 5 failures.
49.hmac_stress_all_with_rand_reset.106290195297998837432094599708797195393087727843737026791977360309358200546592
Line 18056, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/49.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2756892300 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 1406221849 [0x53d13e19])
UVM_INFO @ 2756892300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
63.hmac_stress_all_with_rand_reset.113426864309713039479485998887314523608519730050553428142855055841924570355554
Line 1698, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/63.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 340526667 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 1571707336 [0x5dae59c8])
UVM_INFO @ 340526667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (hmac_scoreboard.sv:635) [scoreboard] Check failed cfg.hmac_vif.is_idle() == val (* [*] vs * [*]) has 1 failures:
25.hmac_stress_all.58006723892006324570044233897431587528402227940133053005243237983239895526326
Line 6760, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/25.hmac_stress_all/latest/run.log
UVM_ERROR @ 2696635756 ps: (hmac_scoreboard.sv:635) [uvm_test_top.env.scoreboard] Check failed cfg.hmac_vif.is_idle() == val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2696635756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---