be3d980075| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.620s | 1.277ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.020s | 53.069us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 1.000s | 32.725us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 11.370s | 2.998ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 6.380s | 1.259ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 14.909m | 174.410ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 1.000s | 32.725us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 6.380s | 1.259ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.149m | 2.223ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 54.480s | 987.075us | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.937m | 94.116ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.470s | 282.900us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.399m | 4.528ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 22.435m | 4.637ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 7.582m | 10.875ms | 8 | 50 | 16.00 |
| V2 | wipe_secret | hmac_wipe_secret | 34.330s | 20.070ms | 0 | 50 | 0.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 56.161m | 85.922ms | 13 | 50 | 26.00 |
| V2 | alert_test | hmac_alert_test | 0.650s | 39.692us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.670s | 36.926us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.230s | 477.396us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.230s | 477.396us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.020s | 53.069us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.000s | 32.725us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 6.380s | 1.259ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.510s | 627.538us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.020s | 53.069us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.000s | 32.725us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 6.380s | 1.259ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.510s | 627.538us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 461 | 590 | 78.14 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.970s | 133.700us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.230s | 857.178us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.230s | 857.178us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.620s | 1.277ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 40.758m | 43.900ms | 3 | 200 | 1.50 |
| V3 | TOTAL | 3 | 200 | 1.50 | |||
| TOTAL | 594 | 920 | 64.57 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 10 | 62.50 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 88.04 | 95.56 | 93.91 | 100.00 | 65.79 | 91.06 | 99.49 | 70.47 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 116 failures:
0.hmac_stress_all_with_rand_reset.78601096713139664888352806810761573323746364985009307412807519731973288472053
Line 12860, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 23467647287 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 23467647287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.hmac_stress_all_with_rand_reset.23706682497768202135505705619072083558856886432224065146796749255965024611978
Line 6224, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14754143696 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14754143696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 114 more failures.
UVM_FATAL (hmac_smoke_vseq.sv:139) [hmac_error_vseq] wait timeout occurred! has 40 failures:
0.hmac_error.10272468579871511054286999743330585799670239320718291902768488625900119182381
Line 10878, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_error/latest/run.log
UVM_FATAL @ 14346550606 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 14346550606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.hmac_error.99338887236722562557847102360608621249514199794172405227204175105219110415895
Line 847, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_error/latest/run.log
UVM_FATAL @ 10439565867 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 10439565867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
1.hmac_stress_all_with_rand_reset.52237931513949416773524912202660778928212515988944187905973118978078417258795
Line 11380, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 29638200178 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 29638200178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.hmac_stress_all_with_rand_reset.31496183478703306786876909170079600074838643471900922704668414381229236596739
Line 27559, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11196687607 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 11196687607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
2.hmac_stress_all.82138860086788674424846438168226969097427511711834970339675390305693579280318
Line 31838, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all/latest/run.log
UVM_FATAL @ 29775522734 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 29775522734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.hmac_stress_all.22102678624482610190808335928960859025445882566208120105831317194771967932247
Line 282251, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_stress_all/latest/run.log
UVM_FATAL @ 807963089113 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 807963089113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (hmac_scoreboard.sv:346) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 38 failures:
0.hmac_stress_all.80073727454442050264911500164641845654948662943089101760052613132168325661976
Line 29043, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest/run.log
UVM_ERROR @ 4132227769 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (597491111 [0x239cfda7] vs 4279238043 [0xff0ffd9b])
UVM_INFO @ 4132227769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all.31542428407625852335823955433607867318100578533354259294594097177604267205388
Line 12805, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all/latest/run.log
UVM_ERROR @ 1300426755 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 1045236194 [0x3e4d09e2])
UVM_INFO @ 1300426755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
2.hmac_wipe_secret.93840773932190361631937655522124594990636117763993256373113835110839166720456
Line 1110, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 926108454 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2779174927 [0xa5a6d80f] vs 3192870978 [0xbe4f5842])
UVM_INFO @ 926108454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.hmac_wipe_secret.44075635655422166837418246341853445771413280495542663892388682578303059786120
Line 3670, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 1155718376 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3329117120 [0xc66e4bc0] vs 1303568174 [0x4db2df2e])
UVM_INFO @ 1155718376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
4.hmac_stress_all_with_rand_reset.83904128272901080768165942509203045877981905932811718187439404382651932640923
Line 175802, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20732397319 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3816382857 [0xe3796189] vs 949398609 [0x3896ac51])
UVM_INFO @ 20732397319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.hmac_stress_all_with_rand_reset.57126844623100550583038448299068860211304196160913345331963442225591520332682
Line 42620, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15665102016 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (430775020 [0x19ad1aec] vs 2676354222 [0x9f85ecae])
UVM_INFO @ 15665102016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
UVM_ERROR (hmac_scoreboard.sv:336) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 38 failures:
Test hmac_wipe_secret has 16 failures.
5.hmac_wipe_secret.114711324257117692565079793309114560117833061861766718986203539554337833563417
Line 2856, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 466824806 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (3358617132 [0xc8306e2c] vs 2434264475 [0x9117ed9b])
UVM_INFO @ 466824806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.hmac_wipe_secret.112020961847682992557708977000033316342529532002262615994634012610294247713103
Line 792, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 346739668 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (287674913 [0x11259221] vs 1861320581 [0x6ef17f85])
UVM_INFO @ 346739668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
Test hmac_stress_all has 5 failures.
6.hmac_stress_all.30475831550824171061691857020889544890941711759459522824255926202389054009831
Line 3719, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all/latest/run.log
UVM_ERROR @ 633227385 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2373284414 [0x8d75723e] vs 2824355588 [0xa8583f04])
UVM_INFO @ 633227385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.hmac_stress_all.93624113938244913687363737276867139786385739234451375710624109415970049692832
Line 591, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_stress_all/latest/run.log
UVM_ERROR @ 22576760 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1346064058 [0x503b4eba] vs 592297305 [0x234dbd59])
UVM_INFO @ 22576760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test hmac_error has 2 failures.
24.hmac_error.105692898219650280946213736016454102963071671252101257046753310502069051139142
Line 4538, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/24.hmac_error/latest/run.log
UVM_ERROR @ 378870460 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3571528962 [0xd4e13502])
UVM_INFO @ 378870460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.hmac_error.108695632864407766351123200395922397868737473122628060652202617347825185710406
Line 2236, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/26.hmac_error/latest/run.log
UVM_ERROR @ 495550618 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 838222986 [0x31f6448a])
UVM_INFO @ 495550618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 15 failures.
57.hmac_stress_all_with_rand_reset.106903167568819593951144902128852436090796861577863668670622110880623406122590
Line 4900, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/57.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1954969932 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (765792063 [0x2da50f3f] vs 2201499288 [0x83383698])
UVM_INFO @ 1954969932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
60.hmac_stress_all_with_rand_reset.65467022085105635193054245584100059969763578897821910710963848003929286355375
Line 81366, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/60.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18723426959 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (341742869 [0x145e9515] vs 1758296009 [0x68cd77c9])
UVM_INFO @ 18723426959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (hmac_scoreboard.sv:333) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 36 failures:
Test hmac_wipe_secret has 13 failures.
0.hmac_wipe_secret.85944024941019048610059600001283981651173317212671176975301170812392541757324
Line 1291, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 1342547284 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1301194067 [0x4d8ea553] vs 3588075937 [0xd5ddb1a1])
UVM_INFO @ 1342547284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_wipe_secret.11823423901896747988911995695504816825934572869533735708714505606801726677830
Line 1278, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 227756783 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (947753282 [0x387d9142] vs 1161611897 [0x453cca79])
UVM_INFO @ 227756783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Test hmac_error has 1 failures.
1.hmac_error.67746229348743622439030031700023109621398765667303008309444607336960490569438
Line 10548, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_error/latest/run.log
UVM_ERROR @ 5470376568 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 1629344504 [0x611dd2f8])
UVM_INFO @ 5470376568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all has 3 failures.
29.hmac_stress_all.5294578477258139656719355921897261341803470519063320566189837309795649163401
Line 4608, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/29.hmac_stress_all/latest/run.log
UVM_ERROR @ 2685791225 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3729454845 [0xde4af6fd] vs 1785740698 [0x6a703d9a])
UVM_INFO @ 2685791225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.hmac_stress_all.12294266140772508078755481058556716264786638428082565042134492792201933432361
Line 1903, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/33.hmac_stress_all/latest/run.log
UVM_ERROR @ 109135827 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3312416217 [0xc56f75d9] vs 359022867 [0x15664113])
UVM_INFO @ 109135827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test hmac_stress_all_with_rand_reset has 19 failures.
33.hmac_stress_all_with_rand_reset.26590133123444176953650832647701856192312097378424204330658436653620625996403
Line 1025, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/33.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1747162851 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2540120074 [0x9767280a] vs 1879203815 [0x70025fe7])
UVM_INFO @ 1747162851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.hmac_stress_all_with_rand_reset.97957130450223279954071540292327205052746691395938635009201097716362722537932
Line 4528, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/48.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4702177390 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (851053140 [0x32ba0a54] vs 2766551059 [0xa4e63813])
UVM_INFO @ 4702177390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (hmac_scoreboard.sv:349) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 28 failures:
Test hmac_wipe_secret has 11 failures.
3.hmac_wipe_secret.2253539490057013942441816965210760566557374310431181930431633280567068890828
Line 1373, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 359810299 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (51919820 [0x3183bcc] vs 99947840 [0x5f51540])
UVM_INFO @ 359810299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.hmac_wipe_secret.78626950035883403330820963956800782901057545280615730796490323765414597936233
Line 2012, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 308925143 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2080678839 [0x7c04a3b7] vs 3392650942 [0xca37bebe])
UVM_INFO @ 308925143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
Test hmac_error has 2 failures.
17.hmac_error.41234845263742785121008249382018006892081735699984562838902190438349051425272
Line 9997, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_error/latest/run.log
UVM_ERROR @ 4203372291 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3303047074 [0xc4e07fa2])
UVM_INFO @ 4203372291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.hmac_error.18032839686513665549154987662419341085016458750030232562662408040964854276037
Line 2522, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/47.hmac_error/latest/run.log
UVM_ERROR @ 987370227 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 75278371 [0x47ca823])
UVM_INFO @ 987370227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 8 failures.
18.hmac_stress_all_with_rand_reset.93728775629643950567190610557979847767899972175802578518274264141713850669778
Line 173799, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/18.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 77178531681 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1457532378 [0x56e02dda] vs 2351732382 [0x8c2c969e])
UVM_INFO @ 77178531681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.hmac_stress_all_with_rand_reset.69818044959215682388488833565817949533216442258064591538433845833095144833295
Line 2628, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/21.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 204238957 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (555686664 [0x211f1b08] vs 1231774808 [0x496b6458])
UVM_INFO @ 204238957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test hmac_stress_all has 7 failures.
19.hmac_stress_all.108134974526453029659438518966162910672110769541716082917411738327314889184314
Line 798, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/19.hmac_stress_all/latest/run.log
UVM_ERROR @ 69947075 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1714364037 [0x662f1e85] vs 1288509984 [0x4ccd1a20])
UVM_INFO @ 69947075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.hmac_stress_all.71149705182598980994634690456885614136664071204556775769013153732806880035959
Line 12179, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/28.hmac_stress_all/latest/run.log
UVM_ERROR @ 2792913646 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1773489036 [0x69b54b8c] vs 77977946 [0x4a5d95a])
UVM_INFO @ 2792913646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=*) == * has 17 failures:
4.hmac_stress_all.13338403355442179845472243859143628987198009137506514720215811910465474893365
Line 55433, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all/latest/run.log
UVM_FATAL @ 20345754820 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x198f0000) == 0x1
UVM_INFO @ 20345754820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.hmac_stress_all.49500484404205132988911493095194541635154393663981890915391642866996000522634
Line 194828, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all/latest/run.log
UVM_FATAL @ 118994945703 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xe2418000) == 0x1
UVM_INFO @ 118994945703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
7.hmac_error.41851919956319004065106996785886302565010756436813422735016847464987857443965
Line 341, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_error/latest/run.log
UVM_FATAL @ 10058252435 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x1133a000) == 0x1
UVM_INFO @ 10058252435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.hmac_error.99145382506767211631689337248795212587302342608597007643479999172680747754641
Line 28975, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/12.hmac_error/latest/run.log
UVM_FATAL @ 49030334480 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x5134e000) == 0x1
UVM_INFO @ 49030334480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
16.hmac_stress_all_with_rand_reset.54005714533862351543235249623418966310452135211386632083064391507272963431866
Line 5872, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/16.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 13223444376 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x87ba8000) == 0x1
UVM_INFO @ 13223444376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.hmac_stress_all_with_rand_reset.3806927672129760639915309033550521843242873410404273475020522071135147870749
Line 175456, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/22.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 43900121608 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x44716000) == 0x1
UVM_INFO @ 43900121608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (hmac_scoreboard.sv:324) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 7 failures:
2.hmac_error.42958661101333844750147906344323409277472934585873337527716005934372952578206
Line 19509, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_error/latest/run.log
UVM_ERROR @ 130410142460 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3274476161 [0xc32c8a81])
UVM_INFO @ 130410142460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.hmac_error.44999756693608936489742565713350984521484463717611359484842107664489097976498
Line 7769, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_error/latest/run.log
UVM_ERROR @ 5120532536 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3305429832 [0xc504db48])
UVM_INFO @ 5120532536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
46.hmac_stress_all_with_rand_reset.47227097573926527179723993758071530109041289373334806092165725100394033894354
Line 10834, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/46.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 692126634 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 824493119 [0x3124c43f])
UVM_INFO @ 692126634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
139.hmac_stress_all_with_rand_reset.43689700454013437638652018813340775589178913064270623511503537818954117549623
Line 3784, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/139.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5095297248 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3062782594 [0xb68e5a82])
UVM_INFO @ 5095297248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
47.hmac_stress_all.91228666894416528584466565752427163701041630250567094762664720389337235911857
Line 191078, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/47.hmac_stress_all/latest/run.log
UVM_ERROR @ 30015325443 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3227981391 [0xc067164f])
UVM_INFO @ 30015325443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_scoreboard.sv:312) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 3 failures:
3.hmac_stress_all.59804806422989480522204910227301791126105248695601509345097609048728566236460
Line 93440, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all/latest/run.log
UVM_ERROR @ 559028223396 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 559028223396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.hmac_stress_all.104812512288512653777995695424887774675120004938680043989880136896929364758243
Line 79969, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/18.hmac_stress_all/latest/run.log
UVM_ERROR @ 30129751422 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 30129751422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
52.hmac_stress_all_with_rand_reset.114108534710623054009960463552723449920936408805381273635245319678086676671505
Line 16148, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/52.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4297178581 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4297178581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
167.hmac_stress_all_with_rand_reset.60535259388692871033051236522588655886079903574739901302800401674904322429604
Line 1106, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/167.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 583572880 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 583572880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_scoreboard.sv:635) [scoreboard] Check failed cfg.hmac_vif.is_idle() == val (* [*] vs * [*]) has 1 failures:
34.hmac_error.106308849306054575273958845545401763886944572268163554729630016802351478385288
Line 11341, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/34.hmac_error/latest/run.log
UVM_ERROR @ 994884578 ps: (hmac_scoreboard.sv:635) [uvm_test_top.env.scoreboard] Check failed cfg.hmac_vif.is_idle() == val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 994884578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---