1579f6a912| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.220s | 2.584ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.860s | 50.062us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.990s | 66.861us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 17.150s | 17.394ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.120s | 491.365us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 22.760m | 273.045ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.990s | 66.861us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.120s | 491.365us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.209m | 13.733ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 57.720s | 4.048ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.471m | 173.722ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.450s | 148.965us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.184m | 1.314ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 25.963m | 5.282ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 7.739m | 10.882ms | 8 | 50 | 16.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.985m | 8.190ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 50.778m | 250.747ms | 19 | 50 | 38.00 |
| V2 | alert_test | hmac_alert_test | 0.650s | 35.343us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.640s | 137.048us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.520s | 138.238us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.520s | 138.238us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.860s | 50.062us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.990s | 66.861us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.120s | 491.365us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.400s | 443.711us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.860s | 50.062us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.990s | 66.861us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.120s | 491.365us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.400s | 443.711us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 517 | 590 | 87.63 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.010s | 90.262us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.350s | 281.356us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.350s | 281.356us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.220s | 2.584ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.100h | 383.718ms | 6 | 200 | 3.00 |
| V3 | TOTAL | 6 | 200 | 3.00 | |||
| TOTAL | 653 | 920 | 70.98 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 11 | 68.75 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.76 | 95.58 | 93.55 | 100.00 | 76.32 | 91.33 | 99.49 | 72.04 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 148 failures:
0.hmac_stress_all_with_rand_reset.84549021664982811325223906953535883391985983025346800292884324636301131560863
Line 17802, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 67235582082 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 67235582082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.16735404943756073678949004371312370903195539150894949968844297680827564679283
Line 74832, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36892521694 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 36892521694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 146 more failures.
UVM_FATAL (hmac_smoke_vseq.sv:139) [hmac_error_vseq] wait timeout occurred! has 66 failures:
0.hmac_error.92548252806842085202513680059223681099351713758363823753831421375897224164142
Line 10745, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_error/latest/run.log
UVM_FATAL @ 13698574503 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 13698574503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_error.13264344101316977026156323911044532449126881739888181033280921483702996405230
Line 15842, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_error/latest/run.log
UVM_FATAL @ 53248153586 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 53248153586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
2.hmac_stress_all.7017662243739598264336494898550893421405392484385999668831735542365829835740
Line 63443, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all/latest/run.log
UVM_FATAL @ 33937438087 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 33937438087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.hmac_stress_all.92417162216133683508913927074854860154604172835355800552280657404547045451119
Line 86852, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all/latest/run.log
UVM_FATAL @ 25473103957 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 25473103957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
15.hmac_stress_all_with_rand_reset.28036195749207278243218099295633342878976415008972892877984057406300362795543
Line 4095, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/15.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 23721209560 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 23721209560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.hmac_stress_all_with_rand_reset.6559060962365408265150950296925778702547534450650749826248272153252159980918
Line 110468, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/20.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 50644753472 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 50644753472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (hmac_scoreboard.sv:299) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 12 failures:
1.hmac_stress_all.107195320981351844040859140923557417145545173022605799442154233116845506309723
Line 11117, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all/latest/run.log
UVM_ERROR @ 1547614851 ps: (hmac_scoreboard.sv:299) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 1547614851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.hmac_stress_all.76781417635822556576603353874973295773060943012526501015567120758329197938124
Line 167288, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_stress_all/latest/run.log
UVM_ERROR @ 538565765705 ps: (hmac_scoreboard.sv:299) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 538565765705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
2.hmac_stress_all_with_rand_reset.4861441516195580913293014384200028070579407477910127175806958741469312532535
Line 5255, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4091155819 ps: (hmac_scoreboard.sv:299) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 4091155819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.hmac_stress_all_with_rand_reset.12094531761824805760330625335036022583674667610287534078405499561014611531947
Line 955, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/26.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15643342409 ps: (hmac_scoreboard.sv:299) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 15643342409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=*) == * has 11 failures:
4.hmac_stress_all.92389082840790063090655887902164863830108810730926044880515969393757796768005
Line 237555, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all/latest/run.log
UVM_FATAL @ 349969744444 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xd0f24000) == 0x1
UVM_INFO @ 349969744444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.hmac_stress_all.108793113293848819386888551024546283622287119270516668905687644239936923747364
Line 157669, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/37.hmac_stress_all/latest/run.log
UVM_FATAL @ 267069750194 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xe99a4000) == 0x1
UVM_INFO @ 267069750194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
8.hmac_error.23624661116390147790414937851962677773377404152820345940026770047508128392167
Line 3968, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_error/latest/run.log
UVM_FATAL @ 11363455690 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x70a5a000) == 0x1
UVM_INFO @ 11363455690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.hmac_error.71529586531323033508601904709426768786996959506352377761884569377809046425721
Line 263, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_error/latest/run.log
UVM_FATAL @ 10023396928 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xa0978000) == 0x1
UVM_INFO @ 10023396928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
29.hmac_stress_all_with_rand_reset.54203905009171856708727207598986087154923793525323981130749664251664406713604
Line 9291, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/29.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 31386153431 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x6acc2000) == 0x1
UVM_INFO @ 31386153431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
88.hmac_stress_all_with_rand_reset.185893891987554162895890345279588843030613368833789342690948431489587539857
Line 38158, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/88.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 19515203316 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x387a6000) == 0x1
UVM_INFO @ 19515203316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_scoreboard.sv:313) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx+*] (* [*] vs * [*]) has 7 failures:
3.hmac_stress_all.63645165848915703302463382767531265480524742701803461057584402616352233700207
Line 167659, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all/latest/run.log
UVM_ERROR @ 38656666228 ps: (hmac_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx+1] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 38656666228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.hmac_stress_all.64165420128997212389984145410610581863076227418492709007427635251952410564795
Line 508, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/20.hmac_stress_all/latest/run.log
UVM_ERROR @ 952757042 ps: (hmac_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx+1] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 952757042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
99.hmac_stress_all_with_rand_reset.112346420663619063430960416631196201156146038559709146369711801031693875648048
Line 8601, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/99.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11601787594 ps: (hmac_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx+1] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 11601787594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
132.hmac_stress_all_with_rand_reset.65696554901176802945954222590865666071481910686502012958552741773689431876819
Line 77998, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/132.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30892801496 ps: (hmac_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx+1] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 30892801496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (hmac_scoreboard.sv:344) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 7 failures:
Test hmac_stress_all has 2 failures.
8.hmac_stress_all.82823282322333875338140287883465179639595983455479526082531489815761880739352
Line 83331, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all/latest/run.log
UVM_ERROR @ 102148442088 ps: (hmac_scoreboard.sv:344) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 3001228975 [0xb2e31eaf])
UVM_INFO @ 102148442088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.hmac_stress_all.93529447261039067258441996744002727946001213599303396342595672680239043567843
Line 228214, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/22.hmac_stress_all/latest/run.log
UVM_ERROR @ 78834568005 ps: (hmac_scoreboard.sv:344) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 3045512739 [0xb586d623])
UVM_INFO @ 78834568005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_error has 2 failures.
43.hmac_error.106924876216313775109161509176033024868735096899524536791727321472457907296185
Line 1547, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/43.hmac_error/latest/run.log
UVM_ERROR @ 282406758 ps: (hmac_scoreboard.sv:344) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 3977935888 [0xed1a7c10])
UVM_INFO @ 282406758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.hmac_error.107458578226136622391392880373732250875486527772728176794283657676801515144656
Line 8990, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/48.hmac_error/latest/run.log
UVM_ERROR @ 6818280315 ps: (hmac_scoreboard.sv:344) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 2725903746 [0xa279fd82])
UVM_INFO @ 6818280315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 3 failures.
70.hmac_stress_all_with_rand_reset.105019059531512219331037444313335079401867570354555061876057239652074749093645
Line 27021, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/70.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7529582244 ps: (hmac_scoreboard.sv:344) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 1985444224 [0x76577980])
UVM_INFO @ 7529582244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
95.hmac_stress_all_with_rand_reset.53205621457702079961875644492983005909356684150644060638475108011366714918739
Line 53877, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/95.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25899087899 ps: (hmac_scoreboard.sv:344) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 1860021209 [0x6eddabd9])
UVM_INFO @ 25899087899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (hmac_scoreboard.sv:320) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 6 failures:
Test hmac_stress_all has 2 failures.
0.hmac_stress_all.89673679302131643799197831261147140422443008888027521249748571458905098968745
Line 5945, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest/run.log
UVM_ERROR @ 1397081365 ps: (hmac_scoreboard.sv:320) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 1397081365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.hmac_stress_all.47898725536539099505804346538780672544894626034786545311178085875853206196775
Line 171099, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/40.hmac_stress_all/latest/run.log
UVM_ERROR @ 98486301466 ps: (hmac_scoreboard.sv:320) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 98486301466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 4 failures.
31.hmac_stress_all_with_rand_reset.111325243651590368442658927195883231104832232334712252700731106668319181420476
Line 17587, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/31.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 61705181671 ps: (hmac_scoreboard.sv:320) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 61705181671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
105.hmac_stress_all_with_rand_reset.103344331409929593520464183209820984129950275955443190461424893234991196943295
Line 27769, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/105.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6163310431 ps: (hmac_scoreboard.sv:320) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 6163310431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (hmac_scoreboard.sv:347) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 6 failures:
Test hmac_stress_all has 2 failures.
17.hmac_stress_all.36646643956451438145207594199095279114398460957965073670632241107632642279923
Line 5367, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_stress_all/latest/run.log
UVM_ERROR @ 12582462115 ps: (hmac_scoreboard.sv:347) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 2840593324 [0xa95003ac])
UVM_INFO @ 12582462115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.hmac_stress_all.46403749805247663214560666411355384441077576745969519283463297971004268559365
Line 368716, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/26.hmac_stress_all/latest/run.log
UVM_ERROR @ 250746557987 ps: (hmac_scoreboard.sv:347) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 1296659062 [0x4d497276])
UVM_INFO @ 250746557987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_error has 1 failures.
29.hmac_error.30955711359093670989341943605789407780380906877201236535914801530225167331601
Line 2025, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/29.hmac_error/latest/run.log
UVM_ERROR @ 752897451 ps: (hmac_scoreboard.sv:347) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 2095409039 [0x7ce5678f])
UVM_INFO @ 752897451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 3 failures.
67.hmac_stress_all_with_rand_reset.36168870296223145988358609518910266506863885231763505249273695176833508516261
Line 31553, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/67.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3837600627 ps: (hmac_scoreboard.sv:347) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 1137314112 [0x43ca0940])
UVM_INFO @ 3837600627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
80.hmac_stress_all_with_rand_reset.40312043186900655167721068087721186240854330470012333700040886118907789408651
Line 28722, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/80.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21175892872 ps: (hmac_scoreboard.sv:347) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 2384742512 [0x8e244870])
UVM_INFO @ 21175892872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (hmac_scoreboard.sv:334) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 3 failures:
Test hmac_error has 1 failures.
25.hmac_error.38128023356729440158712373781391006348045529900680567231016180565291278266899
Line 20445, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/25.hmac_error/latest/run.log
UVM_ERROR @ 83960992892 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 1316203565 [0x4e73ac2d])
UVM_INFO @ 83960992892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 2 failures.
50.hmac_stress_all_with_rand_reset.2980230490089775317424074696263693313829119226317887271336592213750289301020
Line 87801, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/50.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 38986088539 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 2084006025 [0x7c376889])
UVM_INFO @ 38986088539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
72.hmac_stress_all_with_rand_reset.9648130850717306071494405565044387403072901954453368147567052556804936062409
Line 56524, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/72.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20255937057 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3353962831 [0xc7e9694f])
UVM_INFO @ 20255937057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_scoreboard.sv:632) [scoreboard] Check failed cfg.hmac_vif.is_idle() == val (* [*] vs * [*]) has 1 failures:
193.hmac_stress_all_with_rand_reset.91083414251723503900397505891597400513607751541886324865888779878542001678008
Line 10169, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/193.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 52525860794 ps: (hmac_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed cfg.hmac_vif.is_idle() == val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 52525860794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---