HMAC Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	23.680s	4.286ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.020s	45.411us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.990s	35.175us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	14.510s	315.240us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.050s	445.678us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	9.470m	141.643ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.990s	35.175us	20	20	100.00
		hmac_csr_aliasing	9.050s	445.678us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.388m	7.170ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.066m	4.311ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	9.815m	32.404ms	50	50	100.00
		hmac_test_hmac_vectors	1.490s	146.070us	33	50	66.00
V2	burst_wr	hmac_burst_wr	1.624m	6.244ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	20.242m	18.086ms	50	50	100.00
V2	error	hmac_error	3.141m	9.787ms	25	50	50.00
V2	wipe_secret	hmac_wipe_secret	1.581m	2.581ms	46	50	92.00
V2	save_and_restore	save_and_restore			0	0	--
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	wide_digest_configurable_key_length			0	0	--
V2	stress_all	hmac_stress_all	40.494m	245.404ms	21	50	42.00
V2	alert_test	hmac_alert_test	0.750s	28.061us	50	50	100.00
V2	intr_test	hmac_intr_test	0.670s	62.074us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.160s	818.791us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.160s	818.791us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.020s	45.411us	5	5	100.00
		hmac_csr_rw	0.990s	35.175us	20	20	100.00
		hmac_csr_aliasing	9.050s	445.678us	5	5	100.00
		hmac_same_csr_outstanding	2.470s	311.614us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.020s	45.411us	5	5	100.00
		hmac_csr_rw	0.990s	35.175us	20	20	100.00
		hmac_csr_aliasing	9.050s	445.678us	5	5	100.00
		hmac_same_csr_outstanding	2.470s	311.614us	20	20	100.00
V2		TOTAL			515	590	87.29
V2S	tl_intg_err	hmac_sec_cm	1.010s	346.484us	5	5	100.00
		hmac_tl_intg_err	4.490s	1.147ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.490s	1.147ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	23.680s	4.286ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.347h	131.658ms	0	200	0.00
V3		TOTAL			0	200	0.00
		TOTAL			645	920	70.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	13	9	56.25
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.48	95.51	92.26	100.00	63.16	90.61	99.49	71.33

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 129 failures:
- Test hmac_stress_all_with_rand_reset has 129 failures.
  - 0.hmac_stress_all_with_rand_reset.76709995721051530957434016524790895584161216106482081092185385316487440205625
    Line 14402, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18956027548 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18956027548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.hmac_stress_all_with_rand_reset.37416473817521289791242192444383410285871971701410653251457062206675800054801
    Line 19559, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15490739988 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15490739988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 127 more failures.

UVM_ERROR (hmac_scoreboard.sv:325) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 127 failures:

Test hmac_error has 25 failures.

1.hmac_error.111849967125832455194986777524962386019443767986441212621256690329914996235565
Line 7958, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_error/latest/run.log

  UVM_ERROR @ 6782617870 ps: (hmac_scoreboard.sv:325) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2082935051 [0x7c27110b] vs 2922541011 [0xae326fd3])
  UVM_INFO @ 6782617870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.hmac_error.1119280115738370471448322578883225966559078873623646156791359342979304516046
Line 1348, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_error/latest/run.log

  UVM_ERROR @ 1588787362 ps: (hmac_scoreboard.sv:325) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1119439502 [0x42b94a8e] vs 583686440 [0x22ca5928])
  UVM_INFO @ 1588787362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 23 more failures.

Test hmac_test_hmac_vectors has 17 failures.

1.hmac_test_hmac_vectors.50593533276022706400932195407641375808282990171210529696835584181964059608366
Line 339, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_test_hmac_vectors/latest/run.log

  UVM_ERROR @  72699598 ps: (hmac_scoreboard.sv:325) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1494394124 [0x5912a50c] vs 2240970518 [0x85927f16])
  UVM_INFO @  72699598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.hmac_test_hmac_vectors.108733550398780678023653806224587138977669574329397725689798906680589787513701
Line 340, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_test_hmac_vectors/latest/run.log

  UVM_ERROR @  17796041 ps: (hmac_scoreboard.sv:325) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1494394124 [0x5912a50c] vs 2240970518 [0x85927f16])
  UVM_INFO @  17796041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

Test hmac_stress_all has 26 failures.

1.hmac_stress_all.44586371399422308203728689943505044088148367730520772377318042106498337824120
Line 126440, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all/latest/run.log

  UVM_ERROR @ 54121331898 ps: (hmac_scoreboard.sv:325) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2770922639 [0xa528ec8f] vs 3997043258 [0xee3e0a3a])
  UVM_INFO @ 54121331898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.hmac_stress_all.62190970055452693739499781507193009042667537315728648581573594388944713200907
Line 296, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all/latest/run.log

  UVM_ERROR @  30697689 ps: (hmac_scoreboard.sv:325) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (678857706 [0x28768bea] vs 4194053687 [0xf9fc2e37])
  UVM_INFO @  30697689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 24 more failures.

Test hmac_stress_all_with_rand_reset has 59 failures.

4.hmac_stress_all_with_rand_reset.4845517449733806685399339518596646191116298021740785485994399575748406134962
Line 109681, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36972513606 ps: (hmac_scoreboard.sv:325) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (678857706 [0x28768bea] vs 4194053687 [0xf9fc2e37])
  UVM_INFO @ 36972513606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.hmac_stress_all_with_rand_reset.42339136432217682612524480527678901755350436263659574023216186597970581225427
Line 36566, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 33841638936 ps: (hmac_scoreboard.sv:325) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (340414772 [0x144a5134] vs 2151627969 [0x803f3cc1])
  UVM_INFO @ 33841638936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 57 more failures.

UVM_ERROR (hmac_scoreboard.sv:314) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 18 failures:

Test hmac_wipe_secret has 4 failures.

2.hmac_wipe_secret.89840647749827950416839284405406866947437730244834645189657645673840729730802
Line 5861, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_wipe_secret/latest/run.log

  UVM_ERROR @ 1759412682 ps: (hmac_scoreboard.sv:314) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (4197954545 [0xfa37b3f1] vs 4197954545 [0xfa37b3f1])
  UVM_INFO @ 1759412682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.hmac_wipe_secret.56270865514353721376488419817910784369941583563671501380123003878043868861332
Line 1908, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/12.hmac_wipe_secret/latest/run.log

  UVM_ERROR @ 309376971 ps: (hmac_scoreboard.sv:314) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (2019858388 [0x786497d4] vs 2019858388 [0x786497d4])
  UVM_INFO @ 309376971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test hmac_stress_all_with_rand_reset has 11 failures.

12.hmac_stress_all_with_rand_reset.38241824851775903232955555803273251739705409746874154669366269346102220718304
Line 49392, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/12.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 46750762022 ps: (hmac_scoreboard.sv:314) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (2130552822 [0x7efda7f6] vs 2130552822 [0x7efda7f6])
  UVM_INFO @ 46750762022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.hmac_stress_all_with_rand_reset.2440674880345235403966207603897581015460138715780443593639889378454151574914
Line 6196, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/37.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1946686484 ps: (hmac_scoreboard.sv:314) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (3031297152 [0xb4adec80] vs 3031297152 [0xb4adec80])
  UVM_INFO @ 1946686484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test hmac_stress_all has 3 failures.

18.hmac_stress_all.104645456173602720890047690208863193251773512704866738661301693591304958001710
Line 5250, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/18.hmac_stress_all/latest/run.log

  UVM_ERROR @ 1079108259 ps: (hmac_scoreboard.sv:314) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (729072406 [0x2b74c316] vs 729072406 [0x2b74c316])
  UVM_INFO @ 1079108259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.hmac_stress_all.23865946992881329121600100305533952160001674224969556759738940427508144430387
Line 94225, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/20.hmac_stress_all/latest/run.log

  UVM_ERROR @ 30379256161 ps: (hmac_scoreboard.sv:314) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (4216498212 [0xfb52a824] vs 4216498212 [0xfb52a824])
  UVM_INFO @ 30379256161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 129.hmac_stress_all_with_rand_reset.60403359042018971287903906272909475323305296870001739888533257685361761686197
    Line 372, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/129.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 632842396 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 632842396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```