HMAC Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	11.810s	1.935ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.950s	37.366us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.960s	134.415us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.700s	3.203ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.100s	603.368us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.122m	246.798ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.960s	134.415us	20	20	100.00
		hmac_csr_aliasing	8.100s	603.368us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.238m	8.629ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.029m	1.073ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	10.082m	49.238ms	50	50	100.00
		hmac_test_hmac_vectors	1.530s	151.511us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.441m	4.702ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	31.340m	95.916ms	50	50	100.00
V2	error	hmac_error	4.251m	13.920ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.776m	31.094ms	50	50	100.00
V2	save_and_restore	save_and_restore			0	0	--
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	wide_digest_configurable_key_length			0	0	--
V2	stress_all	hmac_stress_all	1.320h	55.082ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.660s	10.845us	50	50	100.00
V2	intr_test	hmac_intr_test	0.700s	13.967us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.660s	328.567us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.660s	328.567us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.950s	37.366us	5	5	100.00
		hmac_csr_rw	0.960s	134.415us	20	20	100.00
		hmac_csr_aliasing	8.100s	603.368us	5	5	100.00
		hmac_same_csr_outstanding	2.660s	806.803us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.950s	37.366us	5	5	100.00
		hmac_csr_rw	0.960s	134.415us	20	20	100.00
		hmac_csr_aliasing	8.100s	603.368us	5	5	100.00
		hmac_same_csr_outstanding	2.660s	806.803us	20	20	100.00
V2		TOTAL			590	590	100.00
V2S	tl_intg_err	hmac_sec_cm	1.280s	577.195us	5	5	100.00
		hmac_tl_intg_err	4.620s	1.116ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.620s	1.116ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	11.810s	1.935ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.740h	120.430ms	11	200	5.50
V3		TOTAL			11	200	5.50
		TOTAL			731	920	79.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	13	13	81.25
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.16	95.60	93.58	100.00	78.95	91.06	99.49	72.47

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 186 failures:
- Test hmac_stress_all_with_rand_reset has 186 failures.
  - 1.hmac_stress_all_with_rand_reset.88334722154224635677182506252421563245266270999351935816855194481533874310975
    Line 7101, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6393859555 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6393859555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.hmac_stress_all_with_rand_reset.51748952787224481430923226139672177131926004989857313666485530490244125065435
    Line 50317, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 465002194569 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 465002194569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 184 more failures.
UVM_ERROR (hmac_scoreboard.sv:314) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 2 failures:
- Test hmac_stress_all_with_rand_reset has 2 failures.
  - 85.hmac_stress_all_with_rand_reset.66546599081429987017805227907153642843493049298690881516388279233728879317403
    Line 48181, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/85.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53155959206 ps: (hmac_scoreboard.sv:314) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 53155959206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 180.hmac_stress_all_with_rand_reset.98146419424533685764521773788131946038816520451788667783692992334673792444911
    Line 325925, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/180.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 742997104990 ps: (hmac_scoreboard.sv:314) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 742997104990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 44.hmac_stress_all_with_rand_reset.108354524898598904331890065745512661826100380057807196848270674763951607997200
    Line 171913, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/44.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35452803857 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 35452803857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0e5093d709`