8cb25a6867| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 12.770s | 2.536ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.010s | 73.022us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.980s | 136.590us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 17.170s | 4.374ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.680s | 558.050us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 15.867m | 564.664ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.980s | 136.590us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.680s | 558.050us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 1.795m | 13.980ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.184m | 4.637ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 10.591m | 73.963ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.520s | 82.094us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.248m | 3.808ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 24.724m | 5.337ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 3.067m | 39.870ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.665m | 1.905ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 1.215h | 32.639ms | 49 | 50 | 98.00 |
| V2 | alert_test | hmac_alert_test | 0.660s | 11.973us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.700s | 50.982us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.090s | 734.516us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.090s | 734.516us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.010s | 73.022us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.980s | 136.590us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.680s | 558.050us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.560s | 334.408us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.010s | 73.022us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.980s | 136.590us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.680s | 558.050us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.560s | 334.408us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 589 | 590 | 99.83 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.010s | 87.032us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.660s | 1.294ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.660s | 1.294ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 12.770s | 2.536ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.701h | 103.218ms | 5 | 200 | 2.50 |
| V3 | TOTAL | 5 | 200 | 2.50 | |||
| TOTAL | 724 | 920 | 78.70 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 12 | 75.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.62 | 95.60 | 93.53 | 100.00 | 76.32 | 91.06 | 99.49 | 71.33 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 194 failures:
0.hmac_stress_all_with_rand_reset.3419679586020452059080910262289427331819529889935978478516939234057960199498
Line 11809, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 37424942430 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 37424942430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.52092196115062844965802444949744502599954821788855102963367123798709120109936
Line 21024, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 38385585282 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 38385585282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 192 more failures.
UVM_ERROR (hmac_scoreboard.sv:314) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 2 failures:
Test hmac_stress_all has 1 failures.
30.hmac_stress_all.44516464436710349801452425418474169948937816635316566126322503738199626074557
Line 141937, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/30.hmac_stress_all/latest/run.log
UVM_ERROR @ 23776314807 ps: (hmac_scoreboard.sv:314) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 23776314807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 1 failures.
108.hmac_stress_all_with_rand_reset.14166327659120092992780423451756933125787275756943882352312363483873436851602
Line 67530, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/108.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5947695941 ps: (hmac_scoreboard.sv:314) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 5947695941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---