HMAC Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	13.190s	2.465ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.070s	136.747us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.960s	19.367us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.400s	5.437ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.870s	764.110us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	6.562m	96.553ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.960s	19.367us	20	20	100.00
		hmac_csr_aliasing	8.870s	764.110us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.163m	114.000ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.215m	5.775ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	9.216m	158.297ms	50	50	100.00
		hmac_test_hmac_vectors	1.490s	83.528us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.285m	1.472ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	20.389m	4.111ms	50	50	100.00
V2	error	hmac_error	4.267m	54.169ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.830m	7.779ms	50	50	100.00
V2	save_and_restore	save_and_restore			0	0	--
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	wide_digest_configurable_key_length			0	0	--
V2	stress_all	hmac_stress_all	1.308h	131.059ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.640s	12.282us	50	50	100.00
V2	intr_test	hmac_intr_test	0.640s	40.130us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.990s	857.090us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.990s	857.090us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.070s	136.747us	5	5	100.00
		hmac_csr_rw	0.960s	19.367us	20	20	100.00
		hmac_csr_aliasing	8.870s	764.110us	5	5	100.00
		hmac_same_csr_outstanding	2.330s	1.825ms	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.070s	136.747us	5	5	100.00
		hmac_csr_rw	0.960s	19.367us	20	20	100.00
		hmac_csr_aliasing	8.870s	764.110us	5	5	100.00
		hmac_same_csr_outstanding	2.330s	1.825ms	20	20	100.00
V2		TOTAL			590	590	100.00
V2S	tl_intg_err	hmac_sec_cm	1.100s	88.474us	5	5	100.00
		hmac_tl_intg_err	4.510s	328.958us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.510s	328.958us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	13.190s	2.465ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.364h	102.656ms	6	200	3.00
V3		TOTAL			6	200	3.00
		TOTAL			726	920	78.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	13	13	81.25
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.30	94.82	92.44	100.00	76.92	89.38	99.49	72.04

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 191 failures:
- Test hmac_stress_all_with_rand_reset has 191 failures.
  - 0.hmac_stress_all_with_rand_reset.91190051264410332592714853385682343573264748262257806523494573414594477397422
    Line 35385, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42732454863 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 42732454863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.hmac_stress_all_with_rand_reset.52055749242039896053471762412268072182696259526770679223240566724713415334007
    Line 308948, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 181119628798 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 181119628798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 189 more failures.
UVM_ERROR (cip_base_vseq.sv:752) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test hmac_stress_all_with_rand_reset has 2 failures.
  - 96.hmac_stress_all_with_rand_reset.6227571857289772460126697533019341419778536102813924525334125163917862460899
    Line 263, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/96.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  37857216 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  37857216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 169.hmac_stress_all_with_rand_reset.107641710379399287350055891294140382334794255085632421285613190089146528137514
    Line 42004, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/169.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31900771134 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 31900771134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_scoreboard.sv:320) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 190.hmac_stress_all_with_rand_reset.50602919005444456616313998451810312914366822062930179550903971352716610887551
    Line 28974, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/190.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 93718651349 ps: (hmac_scoreboard.sv:320) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 93718651349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `01a208901a`