a182fcef27| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 16.930s | 4.099ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.040s | 69.288us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.950s | 56.394us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 16.550s | 9.810ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.990s | 456.645us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 13.859m | 84.059ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.950s | 56.394us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.990s | 456.645us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.192m | 6.643ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.037m | 1.138ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.148m | 88.922ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.470s | 34.438us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.521m | 69.851ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 15.981m | 13.773ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 4.179m | 18.983ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.625m | 90.675ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 1.358h | 106.682ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.640s | 11.427us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.650s | 12.994us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.060s | 79.494us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.060s | 79.494us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.040s | 69.288us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.950s | 56.394us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.990s | 456.645us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.500s | 607.625us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.040s | 69.288us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.950s | 56.394us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.990s | 456.645us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.500s | 607.625us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.010s | 358.300us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.920s | 1.107ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.920s | 1.107ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 16.930s | 4.099ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 2.975h | 87.798ms | 6 | 200 | 3.00 |
| V3 | TOTAL | 6 | 200 | 3.00 | |||
| TOTAL | 726 | 920 | 78.91 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 88.87 | 94.82 | 92.29 | 100.00 | 74.36 | 89.38 | 99.49 | 71.75 |
UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 192 failures:
0.hmac_stress_all_with_rand_reset.106670063282011284630499850302234914753376867017092419237386042571579609233413
Line 10925, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15757887967 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15757887967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.39147851544847476703774394619917762862591891260149402128316430520488403022763
Line 2110, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2719983165 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2719983165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 190 more failures.
UVM_ERROR (cip_base_vseq.sv:752) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
155.hmac_stress_all_with_rand_reset.12211680574066081146322910369502325576385331775213235917597729568783720039759
Line 11486, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/155.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19865263281 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 19865263281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job hmac-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
156.hmac_stress_all_with_rand_reset.23292854669219916710992713595912535038593812041914870302980731501213021747392
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/156.hmac_stress_all_with_rand_reset/latest/run.log
Job ID: smart:dc459a1f-cabd-465b-a584-53beeaf19f91