b29ffbb03c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 14.630s | 3.512ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.000s | 207.513us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 1.010s | 84.577us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 11.500s | 11.813ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.930s | 1.159ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 23.700m | 131.669ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 1.010s | 84.577us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.930s | 1.159ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.314m | 39.966ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.093m | 2.395ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.721m | 202.272ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.460s | 303.023us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.039m | 12.050ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 25.007m | 21.531ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 3.416m | 62.106ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.600m | 15.215ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 1.236h | 551.163ms | 49 | 50 | 98.00 |
| V2 | alert_test | hmac_alert_test | 0.690s | 28.043us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.670s | 139.929us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 3.830s | 181.607us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 3.830s | 181.607us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.000s | 207.513us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.010s | 84.577us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.930s | 1.159ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.450s | 141.535us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.000s | 207.513us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.010s | 84.577us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.930s | 1.159ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.450s | 141.535us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 589 | 590 | 99.83 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.250s | 494.613us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.810s | 554.737us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.810s | 554.737us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 14.630s | 3.512ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 2.789h | 395.632ms | 7 | 200 | 3.50 |
| V3 | TOTAL | 7 | 200 | 3.50 | |||
| TOTAL | 726 | 920 | 78.91 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 12 | 75.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 88.91 | 94.82 | 92.29 | 100.00 | 74.36 | 89.38 | 99.49 | 72.04 |
UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 193 failures:
0.hmac_stress_all_with_rand_reset.72320116060739357640892372726714834703118973868004010420284218411102788856228
Line 55928, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 17802953899 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 17802953899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.17943431236085006893583382127694379100887548840686965631785241513778316461419
Line 134501, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 156089012725 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 156089012725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 191 more failures.
UVM_ERROR (hmac_scoreboard.sv:320) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 1 failures:
39.hmac_stress_all.55718579998835405278915984203940679193754479951741019386494780512287571782779
Line 243804, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/39.hmac_stress_all/latest/run.log
UVM_ERROR @ 283297965692 ps: (hmac_scoreboard.sv:320) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 283297965692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---