32d52b8d41| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 13.790s | 4.485ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.910s | 30.193us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.990s | 81.759us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 16.250s | 4.434ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.900s | 881.820us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 15.221m | 297.709ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.990s | 81.759us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.900s | 881.820us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.534m | 35.859ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.050m | 4.539ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.894m | 88.466ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.550s | 333.907us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.152m | 3.179ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 22.614m | 21.179ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 3.839m | 18.137ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.725m | 28.056ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 1.178h | 2.352s | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.650s | 17.556us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.680s | 14.214us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.520s | 245.558us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.520s | 245.558us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.910s | 30.193us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.990s | 81.759us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.900s | 881.820us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.300s | 112.463us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.910s | 30.193us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.990s | 81.759us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.900s | 881.820us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.300s | 112.463us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.040s | 448.006us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.530s | 333.015us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.530s | 333.015us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 13.790s | 4.485ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 2.253h | 883.897ms | 11 | 200 | 5.50 |
| V3 | TOTAL | 11 | 200 | 5.50 | |||
| TOTAL | 731 | 920 | 79.46 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 88.90 | 94.82 | 92.25 | 100.00 | 74.36 | 89.38 | 99.49 | 72.04 |
UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 187 failures:
0.hmac_stress_all_with_rand_reset.95685753760332908252027444421362912532600811519110455304355070562157326958226
Line 31644, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10633496075 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10633496075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.54970420660220893561895586291052528555410117306752408231191878421255451210918
Line 344572, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30256122946 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 30256122946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 185 more failures.
UVM_ERROR (cip_base_vseq.sv:752) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
61.hmac_stress_all_with_rand_reset.292189475115358550558002760330084108991437320705840774361470955773219397889
Line 340, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/61.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1702721824 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1702721824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
97.hmac_stress_all_with_rand_reset.9183275242679584657945516196561429877734832853689415440897238066025008258662
Line 65074, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/97.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12112804498 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 12112804498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---