302b24f3c6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 15.210s | 5.329ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.960s | 66.735us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 1.010s | 55.204us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 10.660s | 1.445ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.990s | 538.542us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 12.966m | 54.857ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 1.010s | 55.204us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.990s | 538.542us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.584m | 39.829ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.029m | 2.563ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 10.262m | 195.127ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.460s | 331.363us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.306m | 43.609ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 23.899m | 19.287ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 4.524m | 30.177ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.664m | 57.039ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 1.416h | 666.137ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.650s | 75.053us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.670s | 17.390us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 3.990s | 77.243us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 3.990s | 77.243us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.960s | 66.735us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.010s | 55.204us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.990s | 538.542us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.320s | 49.040us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.960s | 66.735us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.010s | 55.204us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.990s | 538.542us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.320s | 49.040us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.110s | 270.818us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.510s | 531.578us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.510s | 531.578us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 15.210s | 5.329ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.863h | 200.529ms | 10 | 200 | 5.00 |
| V3 | TOTAL | 10 | 200 | 5.00 | |||
| TOTAL | 730 | 920 | 79.35 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 88.55 | 94.84 | 92.14 | 100.00 | 71.79 | 89.38 | 99.49 | 72.18 |
UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 188 failures:
0.hmac_stress_all_with_rand_reset.52976850539756784340144571333627937002218261494703315844597606281661889050455
Line 5988, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 34206365462 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 34206365462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.hmac_stress_all_with_rand_reset.58014966742126384163691380524277862231607226152482283636908131433066694365913
Line 12384, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3266845316 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3266845316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 186 more failures.
UVM_ERROR (cip_base_vseq.sv:752) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
77.hmac_stress_all_with_rand_reset.110200357887982177334496911117889116177952721667100024724159973844760697411471
Line 710841, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/77.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 200529217654 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 200529217654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
112.hmac_stress_all_with_rand_reset.93300999368185319514786152066241736446555615813275571983326882638201836070702
Line 294, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/112.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 91476589 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 91476589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---