HMAC Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: f92a5ee77b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	34.700s	11.316ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.960s	22.890us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.000s	93.650us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.470s	1.098ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.340s	5.041ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	19.341m	115.693ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.000s	93.650us	20	20	100.00
		hmac_csr_aliasing	9.340s	5.041ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.432m	14.207ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.244m	8.534ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	9.857m	43.307ms	50	50	100.00
		hmac_test_hmac_vectors	1.450s	216.025us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.342m	15.593ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	25.904m	45.004ms	50	50	100.00
V2	error	hmac_error	3.578m	31.820ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.902m	44.506ms	50	50	100.00
V2	save_and_restore	save_and_restore			0	0	--
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	wide_digest_configurable_key_length			0	0	--
V2	stress_all	hmac_stress_all	1.629h	227.507ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.640s	15.393us	50	50	100.00
V2	intr_test	hmac_intr_test	0.740s	13.747us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.620s	1.284ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.620s	1.284ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.960s	22.890us	5	5	100.00
		hmac_csr_rw	1.000s	93.650us	20	20	100.00
		hmac_csr_aliasing	9.340s	5.041ms	5	5	100.00
		hmac_same_csr_outstanding	2.580s	309.862us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.960s	22.890us	5	5	100.00
		hmac_csr_rw	1.000s	93.650us	20	20	100.00
		hmac_csr_aliasing	9.340s	5.041ms	5	5	100.00
		hmac_same_csr_outstanding	2.580s	309.862us	20	20	100.00
V2		TOTAL			590	590	100.00
V2S	tl_intg_err	hmac_sec_cm	1.030s	223.558us	5	5	100.00
		hmac_tl_intg_err	4.250s	241.230us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.250s	241.230us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	34.700s	11.316ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.842h	137.863ms	9	200	4.50
V3		TOTAL			9	200	4.50
		TOTAL			729	920	79.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	13	13	81.25
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.85	94.84	92.25	100.00	74.36	89.38	99.49	71.61

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 190 failures:
  • Test hmac_stress_all_with_rand_reset has 190 failures.

    • 0.hmac_stress_all_with_rand_reset.19565765577802271131344291479379217758576949752830057595626548224698277985725
      Line 32661, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35705429459 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 35705429459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.hmac_stress_all_with_rand_reset.100259544263244348376382518430258848763814847657542444877898833382614543766199
      Line 19269, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3081072269 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3081072269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 188 more failures.

• UVM_ERROR (cip_base_vseq.sv:752) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 150.hmac_stress_all_with_rand_reset.102782358792326143028084111699399539623127764416341000556939281839383154423957
      Line 307, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/150.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 420055279 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 420055279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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