HMAC Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.090s	4.949ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.010s	71.570us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.000s	68.577us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	9.770s	861.789us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.310s	1.814ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.834m	128.847ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.000s	68.577us	20	20	100.00
		hmac_csr_aliasing	8.310s	1.814ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.140m	76.782ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.118m	24.743ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	10.205m	212.670ms	50	50	100.00
		hmac_test_hmac_vectors	1.460s	112.756us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.228m	2.577ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	21.389m	19.639ms	50	50	100.00
V2	error	hmac_error	3.757m	31.660ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.973m	133.458ms	50	50	100.00
V2	save_and_restore	save_and_restore			0	0	--
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	wide_digest_configurable_key_length			0	0	--
V2	stress_all	hmac_stress_all	1.203h	153.517ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.670s	16.534us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	24.077us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.540s	872.400us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.540s	872.400us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.010s	71.570us	5	5	100.00
		hmac_csr_rw	1.000s	68.577us	20	20	100.00
		hmac_csr_aliasing	8.310s	1.814ms	5	5	100.00
		hmac_same_csr_outstanding	2.420s	559.119us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.010s	71.570us	5	5	100.00
		hmac_csr_rw	1.000s	68.577us	20	20	100.00
		hmac_csr_aliasing	8.310s	1.814ms	5	5	100.00
		hmac_same_csr_outstanding	2.420s	559.119us	20	20	100.00
V2		TOTAL			590	590	100.00
V2S	tl_intg_err	hmac_sec_cm	1.030s	477.755us	5	5	100.00
		hmac_tl_intg_err	4.590s	1.693ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.590s	1.693ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.090s	4.949ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.415h	58.803ms	5	200	2.50
V3		TOTAL			5	200	2.50
		TOTAL			725	920	78.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	13	13	81.25
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.26	94.84	92.14	100.00	76.92	89.38	99.49	72.04

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 195 failures:
  • Test hmac_stress_all_with_rand_reset has 195 failures.

    • 0.hmac_stress_all_with_rand_reset.6575083363529996655943460060491187693875497520766972963499140783124998931678
      Line 357, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1943252901 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1943252901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.hmac_stress_all_with_rand_reset.37231405216430048368436015161982955107084602916785439414938829962374023844321
      Line 23775, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32332775022 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 32332775022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 193 more failures.

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