HMAC Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: eb56ef55d0

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 15.480s 928.471us 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.980s 33.686us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.960s 642.766us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 15.370s 5.238ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 8.860s 855.712us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 16.633m 66.093ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.960s 642.766us 20 20 100.00
hmac_csr_aliasing 8.860s 855.712us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 3.717m 152.142ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.667m 1.738ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 10.399m 21.818ms 5 5 100.00
hmac_test_sha384_vectors 39.553m 141.558ms 5 5 100.00
hmac_test_sha512_vectors 39.367m 182.641ms 4 5 80.00
hmac_test_hmac_vectors 0 0 --
V2 burst_wr hmac_burst_wr 1.724m 32.914ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 32.481m 8.713ms 50 50 100.00
V2 error hmac_error 4.309m 22.001ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.245m 42.144ms 50 50 100.00
V2 save_and_restore hmac_smoke 15.480s 928.471us 50 50 100.00
hmac_long_msg 3.717m 152.142ms 50 50 100.00
hmac_back_pressure 1.667m 1.738ms 50 50 100.00
hmac_datapath_stress 32.481m 8.713ms 50 50 100.00
hmac_burst_wr 1.724m 32.914ms 50 50 100.00
hmac_stress_all 1.174h 24.480ms 50 50 100.00
V2 fifo_empty_status_interrupt fifo_empty_status_interrupt 0 0 --
V2 wide_digest_configurable_key_length hmac_smoke 15.480s 928.471us 50 50 100.00
hmac_long_msg 3.717m 152.142ms 50 50 100.00
hmac_back_pressure 1.667m 1.738ms 50 50 100.00
hmac_datapath_stress 32.481m 8.713ms 50 50 100.00
hmac_burst_wr 1.724m 32.914ms 50 50 100.00
hmac_error 4.309m 22.001ms 50 50 100.00
hmac_wipe_secret 2.245m 42.144ms 50 50 100.00
hmac_test_sha256_vectors 10.399m 21.818ms 5 5 100.00
hmac_test_sha384_vectors 39.553m 141.558ms 5 5 100.00
hmac_test_sha512_vectors 39.367m 182.641ms 4 5 80.00
hmac_stress_all 1.174h 24.480ms 50 50 100.00
hmac_test_hmac_vectors 0 0 --
V2 stress_all hmac_stress_all 1.174h 24.480ms 50 50 100.00
V2 alert_test hmac_alert_test 0.670s 42.326us 50 50 100.00
V2 intr_test hmac_intr_test 0.700s 31.379us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.070s 207.029us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.070s 207.029us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.980s 33.686us 5 5 100.00
hmac_csr_rw 0.960s 642.766us 20 20 100.00
hmac_csr_aliasing 8.860s 855.712us 5 5 100.00
hmac_same_csr_outstanding 2.490s 611.194us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.980s 33.686us 5 5 100.00
hmac_csr_rw 0.960s 642.766us 20 20 100.00
hmac_csr_aliasing 8.860s 855.712us 5 5 100.00
hmac_same_csr_outstanding 2.490s 611.194us 20 20 100.00
V2 TOTAL 504 505 99.80
V2S tl_intg_err hmac_sec_cm 1.000s 314.863us 5 5 100.00
hmac_tl_intg_err 4.290s 806.891us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.290s 806.891us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 15.480s 928.471us 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.575h 115.293ms 10 10 100.00
V3 TOTAL 10 10 100.00
Unmapped tests hmac_test_hmac256_vectors 1.392m 7.312ms 5 5 100.00
hmac_test_hmac384_vectors 1.566m 35.755ms 5 5 100.00
hmac_test_hmac512_vectors 2.027m 192.872ms 5 5 100.00
TOTAL 659 660 99.85

Testplan Progress

Items Total Written Passing Progress
N.A. 3 3 3 100.00
V1 6 6 6 100.00
V2 16 14 13 81.25
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.09 95.95 94.35 100.00 87.18 92.33 99.49 96.35

Failure Buckets

Past Results