HMAC Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 16.640s 1.373ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.070s 42.621us 5 5 100.00
V1 csr_rw hmac_csr_rw 1.030s 36.327us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 17.090s 1.648ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 9.060s 476.787us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 19.786m 705.798ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.030s 36.327us 20 20 100.00
hmac_csr_aliasing 9.060s 476.787us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 3.507m 11.904ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.771m 7.139ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 10.890m 50.694ms 5 5 100.00
hmac_test_sha384_vectors 44.713m 557.238ms 5 5 100.00
hmac_test_sha512_vectors 41.654m 140.812ms 5 5 100.00
hmac_test_hmac_vectors 0 0 --
V2 burst_wr hmac_burst_wr 1.238m 5.878ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 29.395m 7.770ms 50 50 100.00
V2 error hmac_error 3.481m 23.602ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.179m 9.610ms 50 50 100.00
V2 save_and_restore hmac_smoke 16.640s 1.373ms 50 50 100.00
hmac_long_msg 3.507m 11.904ms 50 50 100.00
hmac_back_pressure 1.771m 7.139ms 50 50 100.00
hmac_datapath_stress 29.395m 7.770ms 50 50 100.00
hmac_burst_wr 1.238m 5.878ms 50 50 100.00
hmac_stress_all 56.460m 190.168ms 49 50 98.00
V2 fifo_empty_status_interrupt fifo_empty_status_interrupt 0 0 --
V2 wide_digest_configurable_key_length hmac_smoke 16.640s 1.373ms 50 50 100.00
hmac_long_msg 3.507m 11.904ms 50 50 100.00
hmac_back_pressure 1.771m 7.139ms 50 50 100.00
hmac_datapath_stress 29.395m 7.770ms 50 50 100.00
hmac_burst_wr 1.238m 5.878ms 50 50 100.00
hmac_error 3.481m 23.602ms 50 50 100.00
hmac_wipe_secret 2.179m 9.610ms 50 50 100.00
hmac_test_sha256_vectors 10.890m 50.694ms 5 5 100.00
hmac_test_sha384_vectors 44.713m 557.238ms 5 5 100.00
hmac_test_sha512_vectors 41.654m 140.812ms 5 5 100.00
hmac_stress_all 56.460m 190.168ms 49 50 98.00
hmac_test_hmac_vectors 0 0 --
V2 stress_all hmac_stress_all 56.460m 190.168ms 49 50 98.00
V2 alert_test hmac_alert_test 0.690s 17.830us 50 50 100.00
V2 intr_test hmac_intr_test 0.680s 46.571us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.620s 442.734us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.620s 442.734us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.070s 42.621us 5 5 100.00
hmac_csr_rw 1.030s 36.327us 20 20 100.00
hmac_csr_aliasing 9.060s 476.787us 5 5 100.00
hmac_same_csr_outstanding 2.460s 719.551us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.070s 42.621us 5 5 100.00
hmac_csr_rw 1.030s 36.327us 20 20 100.00
hmac_csr_aliasing 9.060s 476.787us 5 5 100.00
hmac_same_csr_outstanding 2.460s 719.551us 20 20 100.00
V2 TOTAL 504 505 99.80
V2S tl_intg_err hmac_sec_cm 1.000s 83.785us 5 5 100.00
hmac_tl_intg_err 4.280s 277.808us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.280s 277.808us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 16.640s 1.373ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.822h 801.131ms 9 10 90.00
V3 TOTAL 9 10 90.00
Unmapped tests hmac_test_hmac256_vectors 1.026m 3.222ms 5 5 100.00
hmac_test_hmac384_vectors 1.579m 2.426ms 5 5 100.00
hmac_test_hmac512_vectors 2.147m 11.104ms 5 5 100.00
TOTAL 658 660 99.70

Testplan Progress

Items Total Written Passing Progress
N.A. 3 3 3 100.00
V1 6 6 6 100.00
V2 16 14 13 81.25
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.34 95.95 94.24 100.00 82.05 92.33 99.49 96.35

Failure Buckets

Past Results