HMAC Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.060s	1.218ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.890s	32.785us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.000s	527.711us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.080s	1.147ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.350s	451.009us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	18.394m	233.857ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.000s	527.711us	20	20	100.00
		hmac_csr_aliasing	9.350s	451.009us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.701m	4.131ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.993m	2.194ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.623m	495.126ms	5	5	100.00
		hmac_test_sha384_vectors	41.964m	277.534ms	4	5	80.00
		hmac_test_sha512_vectors	40.749m	291.776ms	5	5	100.00
		hmac_test_hmac256_vectors	1.324m	6.950ms	5	5	100.00
		hmac_test_hmac384_vectors	1.503m	12.546ms	5	5	100.00
		hmac_test_hmac512_vectors	2.156m	10.083ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.272m	8.041ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	28.334m	8.055ms	50	50	100.00
V2	error	hmac_error	3.846m	12.441ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.403m	54.045ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.060s	1.218ms	50	50	100.00
		hmac_long_msg	3.701m	4.131ms	50	50	100.00
		hmac_back_pressure	1.993m	2.194ms	50	50	100.00
		hmac_datapath_stress	28.334m	8.055ms	50	50	100.00
		hmac_burst_wr	1.272m	8.041ms	50	50	100.00
		hmac_stress_all	1.359h	56.550ms	50	50	100.00
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	hmac_smoke	16.060s	1.218ms	50	50	100.00
		hmac_long_msg	3.701m	4.131ms	50	50	100.00
		hmac_back_pressure	1.993m	2.194ms	50	50	100.00
		hmac_datapath_stress	28.334m	8.055ms	50	50	100.00
		hmac_burst_wr	1.272m	8.041ms	50	50	100.00
		hmac_error	3.846m	12.441ms	50	50	100.00
		hmac_wipe_secret	2.403m	54.045ms	50	50	100.00
		hmac_test_sha256_vectors	10.623m	495.126ms	5	5	100.00
		hmac_test_sha384_vectors	41.964m	277.534ms	4	5	80.00
		hmac_test_sha512_vectors	40.749m	291.776ms	5	5	100.00
		hmac_test_hmac256_vectors	1.324m	6.950ms	5	5	100.00
		hmac_test_hmac384_vectors	1.503m	12.546ms	5	5	100.00
		hmac_test_hmac512_vectors	2.156m	10.083ms	5	5	100.00
		hmac_stress_all	1.359h	56.550ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.359h	56.550ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.650s	15.953us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	21.018us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.600s	89.660us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.600s	89.660us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.890s	32.785us	5	5	100.00
		hmac_csr_rw	1.000s	527.711us	20	20	100.00
		hmac_csr_aliasing	9.350s	451.009us	5	5	100.00
		hmac_same_csr_outstanding	2.330s	594.501us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.890s	32.785us	5	5	100.00
		hmac_csr_rw	1.000s	527.711us	20	20	100.00
		hmac_csr_aliasing	9.350s	451.009us	5	5	100.00
		hmac_same_csr_outstanding	2.330s	594.501us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.020s	302.889us	5	5	100.00
		hmac_tl_intg_err	4.150s	248.423us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.150s	248.423us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.060s	1.218ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.983h	243.857ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			658	660	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	17	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.52	95.95	94.29	100.00	87.18	92.33	99.49	99.42

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test hmac_test_sha384_vectors has 1 failures.
  - 1.hmac_test_sha384_vectors.67695821004901919770331313446230798766900240648594770235624513186956769302004
    Line 152278, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job hmac-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 7.hmac_stress_all_with_rand_reset.22072387658345818771633097216793602840295354355764455629572358673383621108449
    Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a397d119-642f-4c34-a854-e3841f5214c5
```

HMAC Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `abd7ce57f2`