HMAC Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.850s	1.233ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.940s	22.743us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.980s	214.044us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.620s	385.342us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.150s	1.253ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	9.736m	39.407ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.980s	214.044us	20	20	100.00
		hmac_csr_aliasing	6.150s	1.253ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.626m	37.904ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.103m	2.179ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.043m	11.252ms	5	5	100.00
		hmac_test_sha384_vectors	44.950m	405.958ms	5	5	100.00
		hmac_test_sha512_vectors	44.467m	367.802ms	5	5	100.00
		hmac_test_hmac256_vectors	1.286m	27.635ms	5	5	100.00
		hmac_test_hmac384_vectors	1.793m	27.086ms	5	5	100.00
		hmac_test_hmac512_vectors	2.199m	78.787ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.281m	2.655ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	30.007m	29.551ms	50	50	100.00
V2	error	hmac_error	4.898m	20.907ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.924m	13.314ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.850s	1.233ms	50	50	100.00
		hmac_long_msg	3.626m	37.904ms	50	50	100.00
		hmac_back_pressure	2.103m	2.179ms	50	50	100.00
		hmac_datapath_stress	30.007m	29.551ms	50	50	100.00
		hmac_burst_wr	1.281m	2.655ms	50	50	100.00
		hmac_stress_all	1.568h	224.119ms	49	50	98.00
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	hmac_smoke	16.850s	1.233ms	50	50	100.00
		hmac_long_msg	3.626m	37.904ms	50	50	100.00
		hmac_back_pressure	2.103m	2.179ms	50	50	100.00
		hmac_datapath_stress	30.007m	29.551ms	50	50	100.00
		hmac_burst_wr	1.281m	2.655ms	50	50	100.00
		hmac_error	4.898m	20.907ms	50	50	100.00
		hmac_wipe_secret	2.924m	13.314ms	50	50	100.00
		hmac_test_sha256_vectors	11.043m	11.252ms	5	5	100.00
		hmac_test_sha384_vectors	44.950m	405.958ms	5	5	100.00
		hmac_test_sha512_vectors	44.467m	367.802ms	5	5	100.00
		hmac_test_hmac256_vectors	1.286m	27.635ms	5	5	100.00
		hmac_test_hmac384_vectors	1.793m	27.086ms	5	5	100.00
		hmac_test_hmac512_vectors	2.199m	78.787ms	5	5	100.00
		hmac_stress_all	1.568h	224.119ms	49	50	98.00
V2	stress_all	hmac_stress_all	1.568h	224.119ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.650s	12.564us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	29.961us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.680s	211.462us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.680s	211.462us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.940s	22.743us	5	5	100.00
		hmac_csr_rw	0.980s	214.044us	20	20	100.00
		hmac_csr_aliasing	6.150s	1.253ms	5	5	100.00
		hmac_same_csr_outstanding	2.520s	552.555us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.940s	22.743us	5	5	100.00
		hmac_csr_rw	0.980s	214.044us	20	20	100.00
		hmac_csr_aliasing	6.150s	1.253ms	5	5	100.00
		hmac_same_csr_outstanding	2.520s	552.555us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.020s	159.492us	5	5	100.00
		hmac_tl_intg_err	4.520s	1.405ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.520s	1.405ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.850s	1.233ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.583h	348.179ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			659	660	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	17	16	88.89
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.15	95.95	94.24	100.00	84.62	92.33	99.49	99.42

Failure Buckets

UVM_ERROR (hmac_scoreboard.sv:422) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all has 1 failures.
  - 7.hmac_stress_all.84026740762585319848205928441287195142249041701323944239393116745622827067065
    Line 50306, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all/latest/run.log
```
  UVM_ERROR @ 24849101722 ps: (hmac_scoreboard.sv:422) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 24849101722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e6706fcc7b`