HMAC Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 15.140s 2.006ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.030s 119.550us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.980s 16.515us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 15.390s 1.057ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 6.190s 2.957ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 11.951m 261.326ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.980s 16.515us 20 20 100.00
hmac_csr_aliasing 6.190s 2.957ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 3.803m 3.995ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.629m 1.591ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 10.321m 142.992ms 5 5 100.00
hmac_test_sha384_vectors 42.082m 196.658ms 5 5 100.00
hmac_test_sha512_vectors 42.893m 385.836ms 5 5 100.00
hmac_test_hmac256_vectors 1.195m 3.524ms 5 5 100.00
hmac_test_hmac384_vectors 1.722m 38.520ms 5 5 100.00
hmac_test_hmac512_vectors 1.965m 7.703ms 5 5 100.00
V2 burst_wr hmac_burst_wr 1.032m 1.095ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 33.146m 115.134ms 50 50 100.00
V2 error hmac_error 4.449m 41.973ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.387m 11.870ms 50 50 100.00
V2 save_and_restore hmac_smoke 15.140s 2.006ms 50 50 100.00
hmac_long_msg 3.803m 3.995ms 50 50 100.00
hmac_back_pressure 1.629m 1.591ms 50 50 100.00
hmac_datapath_stress 33.146m 115.134ms 50 50 100.00
hmac_burst_wr 1.032m 1.095ms 50 50 100.00
hmac_stress_all 1.396h 125.817ms 50 50 100.00
V2 fifo_empty_status_interrupt fifo_empty_status_interrupt 0 0 --
V2 wide_digest_configurable_key_length hmac_smoke 15.140s 2.006ms 50 50 100.00
hmac_long_msg 3.803m 3.995ms 50 50 100.00
hmac_back_pressure 1.629m 1.591ms 50 50 100.00
hmac_datapath_stress 33.146m 115.134ms 50 50 100.00
hmac_burst_wr 1.032m 1.095ms 50 50 100.00
hmac_error 4.449m 41.973ms 50 50 100.00
hmac_wipe_secret 2.387m 11.870ms 50 50 100.00
hmac_test_sha256_vectors 10.321m 142.992ms 5 5 100.00
hmac_test_sha384_vectors 42.082m 196.658ms 5 5 100.00
hmac_test_sha512_vectors 42.893m 385.836ms 5 5 100.00
hmac_test_hmac256_vectors 1.195m 3.524ms 5 5 100.00
hmac_test_hmac384_vectors 1.722m 38.520ms 5 5 100.00
hmac_test_hmac512_vectors 1.965m 7.703ms 5 5 100.00
hmac_stress_all 1.396h 125.817ms 50 50 100.00
V2 stress_all hmac_stress_all 1.396h 125.817ms 50 50 100.00
V2 alert_test hmac_alert_test 0.670s 25.662us 50 50 100.00
V2 intr_test hmac_intr_test 0.660s 42.911us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.280s 498.626us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.280s 498.626us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.030s 119.550us 5 5 100.00
hmac_csr_rw 0.980s 16.515us 20 20 100.00
hmac_csr_aliasing 6.190s 2.957ms 5 5 100.00
hmac_same_csr_outstanding 2.250s 190.250us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.030s 119.550us 5 5 100.00
hmac_csr_rw 0.980s 16.515us 20 20 100.00
hmac_csr_aliasing 6.190s 2.957ms 5 5 100.00
hmac_same_csr_outstanding 2.250s 190.250us 20 20 100.00
V2 TOTAL 520 520 100.00
V2S tl_intg_err hmac_sec_cm 1.040s 86.770us 5 5 100.00
hmac_tl_intg_err 4.750s 583.025us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.750s 583.025us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 15.140s 2.006ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.002h 2.337s 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 660 660 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 18 17 17 94.44
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.58 95.95 94.24 100.00 87.18 92.33 99.49 99.85

Past Results