HMAC Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	14.930s	1.200ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.010s	316.525us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.970s	35.000us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.190s	312.368us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.020s	629.708us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	12.278m	50.074ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.970s	35.000us	20	20	100.00
		hmac_csr_aliasing	8.020s	629.708us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.659m	16.798ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.842m	1.897ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.978m	49.426ms	5	5	100.00
		hmac_test_sha384_vectors	43.956m	753.918ms	4	5	80.00
		hmac_test_sha512_vectors	43.023m	187.272ms	5	5	100.00
		hmac_test_hmac256_vectors	1.140m	8.679ms	5	5	100.00
		hmac_test_hmac384_vectors	1.579m	11.964ms	5	5	100.00
		hmac_test_hmac512_vectors	2.219m	11.468ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.122m	11.374ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	26.347m	7.345ms	50	50	100.00
V2	error	hmac_error	3.873m	13.419ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.605m	9.169ms	50	50	100.00
V2	save_and_restore	hmac_smoke	14.930s	1.200ms	50	50	100.00
		hmac_long_msg	3.659m	16.798ms	50	50	100.00
		hmac_back_pressure	1.842m	1.897ms	50	50	100.00
		hmac_datapath_stress	26.347m	7.345ms	50	50	100.00
		hmac_burst_wr	1.122m	11.374ms	50	50	100.00
		hmac_stress_all	1.106h	549.045ms	50	50	100.00
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	hmac_smoke	14.930s	1.200ms	50	50	100.00
		hmac_long_msg	3.659m	16.798ms	50	50	100.00
		hmac_back_pressure	1.842m	1.897ms	50	50	100.00
		hmac_datapath_stress	26.347m	7.345ms	50	50	100.00
		hmac_burst_wr	1.122m	11.374ms	50	50	100.00
		hmac_error	3.873m	13.419ms	50	50	100.00
		hmac_wipe_secret	2.605m	9.169ms	50	50	100.00
		hmac_test_sha256_vectors	10.978m	49.426ms	5	5	100.00
		hmac_test_sha384_vectors	43.956m	753.918ms	4	5	80.00
		hmac_test_sha512_vectors	43.023m	187.272ms	5	5	100.00
		hmac_test_hmac256_vectors	1.140m	8.679ms	5	5	100.00
		hmac_test_hmac384_vectors	1.579m	11.964ms	5	5	100.00
		hmac_test_hmac512_vectors	2.219m	11.468ms	5	5	100.00
		hmac_stress_all	1.106h	549.045ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.106h	549.045ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.650s	14.748us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	83.611us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.450s	938.229us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.450s	938.229us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.010s	316.525us	5	5	100.00
		hmac_csr_rw	0.970s	35.000us	20	20	100.00
		hmac_csr_aliasing	8.020s	629.708us	5	5	100.00
		hmac_same_csr_outstanding	2.390s	149.214us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.010s	316.525us	5	5	100.00
		hmac_csr_rw	0.970s	35.000us	20	20	100.00
		hmac_csr_aliasing	8.020s	629.708us	5	5	100.00
		hmac_same_csr_outstanding	2.390s	149.214us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	0.980s	75.850us	5	5	100.00
		hmac_tl_intg_err	4.660s	537.846us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.660s	537.846us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	14.930s	1.200ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.650h	82.560ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			658	660	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	17	16	88.89
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.00	97.15	97.27	100.00	86.84	98.43	99.49	99.85

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test hmac_test_sha384_vectors has 1 failures.
  - 0.hmac_test_sha384_vectors.26535578802631317993209913763795340266979252937697978594699366055019253456915
    Line 108642, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_scoreboard.sv:483) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 9.hmac_stress_all_with_rand_reset.42843517831073414319108296091316816392854467174001912069662061670023431221134
    Line 54895, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38445570065 ps: (hmac_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 38445570065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9edf84e236`