HMAC Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.410s	993.311us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.000s	35.974us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.980s	40.487us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	10.710s	733.091us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.020s	463.848us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.186m	620.077ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.980s	40.487us	20	20	100.00
		hmac_csr_aliasing	9.020s	463.848us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.587m	12.312ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.841m	17.692ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.024m	103.382ms	5	5	100.00
		hmac_test_sha384_vectors	47.457m	928.176ms	4	5	80.00
		hmac_test_sha512_vectors	44.891m	392.374ms	5	5	100.00
		hmac_test_hmac256_vectors	1.260m	22.952ms	5	5	100.00
		hmac_test_hmac384_vectors	1.643m	9.577ms	5	5	100.00
		hmac_test_hmac512_vectors	2.306m	8.352ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.488m	15.436ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	36.409m	18.754ms	50	50	100.00
V2	error	hmac_error	4.279m	19.957ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.468m	10.001ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.410s	993.311us	50	50	100.00
		hmac_long_msg	3.587m	12.312ms	50	50	100.00
		hmac_back_pressure	1.841m	17.692ms	50	50	100.00
		hmac_datapath_stress	36.409m	18.754ms	50	50	100.00
		hmac_burst_wr	1.488m	15.436ms	50	50	100.00
		hmac_stress_all	1.272h	231.731ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.410s	993.311us	50	50	100.00
		hmac_long_msg	3.587m	12.312ms	50	50	100.00
		hmac_back_pressure	1.841m	17.692ms	50	50	100.00
		hmac_datapath_stress	36.409m	18.754ms	50	50	100.00
		hmac_wipe_secret	2.468m	10.001ms	50	50	100.00
		hmac_test_sha256_vectors	11.024m	103.382ms	5	5	100.00
		hmac_test_sha384_vectors	47.457m	928.176ms	4	5	80.00
		hmac_test_sha512_vectors	44.891m	392.374ms	5	5	100.00
		hmac_test_hmac256_vectors	1.260m	22.952ms	5	5	100.00
		hmac_test_hmac384_vectors	1.643m	9.577ms	5	5	100.00
		hmac_test_hmac512_vectors	2.306m	8.352ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.410s	993.311us	50	50	100.00
		hmac_long_msg	3.587m	12.312ms	50	50	100.00
		hmac_back_pressure	1.841m	17.692ms	50	50	100.00
		hmac_datapath_stress	36.409m	18.754ms	50	50	100.00
		hmac_burst_wr	1.488m	15.436ms	50	50	100.00
		hmac_error	4.279m	19.957ms	50	50	100.00
		hmac_wipe_secret	2.468m	10.001ms	50	50	100.00
		hmac_test_sha256_vectors	11.024m	103.382ms	5	5	100.00
		hmac_test_sha384_vectors	47.457m	928.176ms	4	5	80.00
		hmac_test_sha512_vectors	44.891m	392.374ms	5	5	100.00
		hmac_test_hmac256_vectors	1.260m	22.952ms	5	5	100.00
		hmac_test_hmac384_vectors	1.643m	9.577ms	5	5	100.00
		hmac_test_hmac512_vectors	2.306m	8.352ms	5	5	100.00
		hmac_stress_all	1.272h	231.731ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.272h	231.731ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.670s	41.820us	50	50	100.00
V2	intr_test	hmac_intr_test	0.670s	15.219us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.500s	499.358us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.500s	499.358us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.000s	35.974us	5	5	100.00
		hmac_csr_rw	0.980s	40.487us	20	20	100.00
		hmac_csr_aliasing	9.020s	463.848us	5	5	100.00
		hmac_same_csr_outstanding	2.660s	160.682us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.000s	35.974us	5	5	100.00
		hmac_csr_rw	0.980s	40.487us	20	20	100.00
		hmac_csr_aliasing	9.020s	463.848us	5	5	100.00
		hmac_same_csr_outstanding	2.660s	160.682us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	0.970s	183.483us	5	5	100.00
		hmac_tl_intg_err	4.760s	1.047ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.760s	1.047ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.410s	993.311us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	36.611m	21.781ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			659	660	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.51	95.26	97.22	100.00	94.12	98.12	97.97	99.85

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test hmac_test_sha384_vectors has 1 failures.
  - 2.hmac_test_sha384_vectors.80913732719059257072457001568158499221599292449330686156939346052195648518738
    Line 196190, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c42c47ec2d`