HMAC Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.740s	1.291ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.000s	22.824us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.060s	143.304us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.320s	3.748ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.000s	302.451us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	3.050s	607.739us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.060s	143.304us	20	20	100.00
		hmac_csr_aliasing	8.000s	302.451us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.414m	19.692ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.719m	1.821ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.875m	179.530ms	5	5	100.00
		hmac_test_sha384_vectors	42.329m	138.026ms	4	5	80.00
		hmac_test_sha512_vectors	43.219m	316.953ms	5	5	100.00
		hmac_test_hmac256_vectors	1.390m	28.708ms	5	5	100.00
		hmac_test_hmac384_vectors	1.694m	16.486ms	5	5	100.00
		hmac_test_hmac512_vectors	2.172m	3.183ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.613m	25.575ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	24.595m	23.723ms	50	50	100.00
V2	error	hmac_error	4.729m	5.133ms	49	50	98.00
V2	wipe_secret	hmac_wipe_secret	2.460m	46.736ms	50	50	100.00
V2	save_and_restore	hmac_smoke	17.740s	1.291ms	50	50	100.00
		hmac_long_msg	4.414m	19.692ms	50	50	100.00
		hmac_back_pressure	1.719m	1.821ms	50	50	100.00
		hmac_datapath_stress	24.595m	23.723ms	50	50	100.00
		hmac_burst_wr	1.613m	25.575ms	50	50	100.00
		hmac_stress_all	1.070h	129.368ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.740s	1.291ms	50	50	100.00
		hmac_long_msg	4.414m	19.692ms	50	50	100.00
		hmac_back_pressure	1.719m	1.821ms	50	50	100.00
		hmac_datapath_stress	24.595m	23.723ms	50	50	100.00
		hmac_wipe_secret	2.460m	46.736ms	50	50	100.00
		hmac_test_sha256_vectors	11.875m	179.530ms	5	5	100.00
		hmac_test_sha384_vectors	42.329m	138.026ms	4	5	80.00
		hmac_test_sha512_vectors	43.219m	316.953ms	5	5	100.00
		hmac_test_hmac256_vectors	1.390m	28.708ms	5	5	100.00
		hmac_test_hmac384_vectors	1.694m	16.486ms	5	5	100.00
		hmac_test_hmac512_vectors	2.172m	3.183ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.740s	1.291ms	50	50	100.00
		hmac_long_msg	4.414m	19.692ms	50	50	100.00
		hmac_back_pressure	1.719m	1.821ms	50	50	100.00
		hmac_datapath_stress	24.595m	23.723ms	50	50	100.00
		hmac_burst_wr	1.613m	25.575ms	50	50	100.00
		hmac_error	4.729m	5.133ms	49	50	98.00
		hmac_wipe_secret	2.460m	46.736ms	50	50	100.00
		hmac_test_sha256_vectors	11.875m	179.530ms	5	5	100.00
		hmac_test_sha384_vectors	42.329m	138.026ms	4	5	80.00
		hmac_test_sha512_vectors	43.219m	316.953ms	5	5	100.00
		hmac_test_hmac256_vectors	1.390m	28.708ms	5	5	100.00
		hmac_test_hmac384_vectors	1.694m	16.486ms	5	5	100.00
		hmac_test_hmac512_vectors	2.172m	3.183ms	5	5	100.00
		hmac_stress_all	1.070h	129.368ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.070h	129.368ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.660s	14.187us	50	50	100.00
V2	intr_test	hmac_intr_test	0.660s	31.586us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.200s	311.016us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.200s	311.016us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.000s	22.824us	5	5	100.00
		hmac_csr_rw	1.060s	143.304us	20	20	100.00
		hmac_csr_aliasing	8.000s	302.451us	5	5	100.00
		hmac_same_csr_outstanding	2.280s	113.688us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.000s	22.824us	5	5	100.00
		hmac_csr_rw	1.060s	143.304us	20	20	100.00
		hmac_csr_aliasing	8.000s	302.451us	5	5	100.00
		hmac_same_csr_outstanding	2.280s	113.688us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	0.950s	65.410us	5	5	100.00
		hmac_tl_intg_err	4.320s	481.705us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.320s	481.705us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.740s	1.291ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.488h	100.015ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			658	660	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.61	95.40	97.17	100.00	94.12	98.27	98.48	99.85

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test hmac_test_sha384_vectors has 1 failures.

    • 0.hmac_test_sha384_vectors.5874789315196223923274450057233942682544555503692063638819152604039041124364
      Line 99628, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test hmac_error has 1 failures.

    • 36.hmac_error.101073981943390650956119844442000333728106861433454144529611388341943792373221
      Line 27122, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/36.hmac_error/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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