HMAC Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 17.890s 1.218ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.020s 43.872us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.960s 34.233us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 15.570s 2.118ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 7.930s 618.520us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 16.661m 73.306ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.960s 34.233us 20 20 100.00
hmac_csr_aliasing 7.930s 618.520us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 3.598m 126.459ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.859m 15.686ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 10.590m 35.863ms 5 5 100.00
hmac_test_sha384_vectors 47.678m 911.241ms 5 5 100.00
hmac_test_sha512_vectors 43.750m 441.195ms 5 5 100.00
hmac_test_hmac256_vectors 1.449m 4.787ms 5 5 100.00
hmac_test_hmac384_vectors 1.684m 4.787ms 5 5 100.00
hmac_test_hmac512_vectors 2.448m 24.167ms 5 5 100.00
V2 burst_wr hmac_burst_wr 1.289m 23.840ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 36.050m 9.172ms 50 50 100.00
V2 error hmac_error 3.769m 39.450ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.755m 12.221ms 50 50 100.00
V2 save_and_restore hmac_smoke 17.890s 1.218ms 50 50 100.00
hmac_long_msg 3.598m 126.459ms 50 50 100.00
hmac_back_pressure 1.859m 15.686ms 50 50 100.00
hmac_datapath_stress 36.050m 9.172ms 50 50 100.00
hmac_burst_wr 1.289m 23.840ms 50 50 100.00
hmac_stress_all 1.054h 85.239ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 17.890s 1.218ms 50 50 100.00
hmac_long_msg 3.598m 126.459ms 50 50 100.00
hmac_back_pressure 1.859m 15.686ms 50 50 100.00
hmac_datapath_stress 36.050m 9.172ms 50 50 100.00
hmac_wipe_secret 2.755m 12.221ms 50 50 100.00
hmac_test_sha256_vectors 10.590m 35.863ms 5 5 100.00
hmac_test_sha384_vectors 47.678m 911.241ms 5 5 100.00
hmac_test_sha512_vectors 43.750m 441.195ms 5 5 100.00
hmac_test_hmac256_vectors 1.449m 4.787ms 5 5 100.00
hmac_test_hmac384_vectors 1.684m 4.787ms 5 5 100.00
hmac_test_hmac512_vectors 2.448m 24.167ms 5 5 100.00
V2 wide_digest_configurable_key_length hmac_smoke 17.890s 1.218ms 50 50 100.00
hmac_long_msg 3.598m 126.459ms 50 50 100.00
hmac_back_pressure 1.859m 15.686ms 50 50 100.00
hmac_datapath_stress 36.050m 9.172ms 50 50 100.00
hmac_burst_wr 1.289m 23.840ms 50 50 100.00
hmac_error 3.769m 39.450ms 50 50 100.00
hmac_wipe_secret 2.755m 12.221ms 50 50 100.00
hmac_test_sha256_vectors 10.590m 35.863ms 5 5 100.00
hmac_test_sha384_vectors 47.678m 911.241ms 5 5 100.00
hmac_test_sha512_vectors 43.750m 441.195ms 5 5 100.00
hmac_test_hmac256_vectors 1.449m 4.787ms 5 5 100.00
hmac_test_hmac384_vectors 1.684m 4.787ms 5 5 100.00
hmac_test_hmac512_vectors 2.448m 24.167ms 5 5 100.00
hmac_stress_all 1.054h 85.239ms 50 50 100.00
V2 stress_all hmac_stress_all 1.054h 85.239ms 50 50 100.00
V2 alert_test hmac_alert_test 0.640s 24.643us 50 50 100.00
V2 intr_test hmac_intr_test 0.710s 52.292us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.100s 1.061ms 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.100s 1.061ms 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.020s 43.872us 5 5 100.00
hmac_csr_rw 0.960s 34.233us 20 20 100.00
hmac_csr_aliasing 7.930s 618.520us 5 5 100.00
hmac_same_csr_outstanding 2.450s 146.766us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.020s 43.872us 5 5 100.00
hmac_csr_rw 0.960s 34.233us 20 20 100.00
hmac_csr_aliasing 7.930s 618.520us 5 5 100.00
hmac_same_csr_outstanding 2.450s 146.766us 20 20 100.00
V2 TOTAL 520 520 100.00
V2S tl_intg_err hmac_sec_cm 1.110s 229.215us 5 5 100.00
hmac_tl_intg_err 4.460s 1.145ms 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.460s 1.145ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 17.890s 1.218ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.160h 247.381ms 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 660 660 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.46 95.40 97.22 100.00 100.00 98.27 98.48 99.85

Past Results