HMAC Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	18.870s	1.441ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.110s	36.558us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.020s	238.700us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	10.700s	1.446ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.170s	2.396ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.954m	117.600ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.020s	238.700us	20	20	100.00
		hmac_csr_aliasing	9.170s	2.396ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.640m	3.872ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.983m	3.933ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.969m	103.954ms	5	5	100.00
		hmac_test_sha384_vectors	46.847m	844.610ms	5	5	100.00
		hmac_test_sha512_vectors	45.924m	1.550s	5	5	100.00
		hmac_test_hmac256_vectors	1.149m	6.635ms	5	5	100.00
		hmac_test_hmac384_vectors	1.653m	6.036ms	5	5	100.00
		hmac_test_hmac512_vectors	2.459m	35.274ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.523m	18.928ms	48	50	96.00
V2	datapath_stress	hmac_datapath_stress	28.350m	72.841ms	50	50	100.00
V2	error	hmac_error	3.817m	18.440ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.506m	65.215ms	50	50	100.00
V2	save_and_restore	hmac_smoke	18.870s	1.441ms	50	50	100.00
		hmac_long_msg	3.640m	3.872ms	50	50	100.00
		hmac_back_pressure	1.983m	3.933ms	50	50	100.00
		hmac_datapath_stress	28.350m	72.841ms	50	50	100.00
		hmac_burst_wr	1.523m	18.928ms	48	50	96.00
		hmac_stress_all	1.570h	240.660ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	18.870s	1.441ms	50	50	100.00
		hmac_long_msg	3.640m	3.872ms	50	50	100.00
		hmac_back_pressure	1.983m	3.933ms	50	50	100.00
		hmac_datapath_stress	28.350m	72.841ms	50	50	100.00
		hmac_wipe_secret	2.506m	65.215ms	50	50	100.00
		hmac_test_sha256_vectors	10.969m	103.954ms	5	5	100.00
		hmac_test_sha384_vectors	46.847m	844.610ms	5	5	100.00
		hmac_test_sha512_vectors	45.924m	1.550s	5	5	100.00
		hmac_test_hmac256_vectors	1.149m	6.635ms	5	5	100.00
		hmac_test_hmac384_vectors	1.653m	6.036ms	5	5	100.00
		hmac_test_hmac512_vectors	2.459m	35.274ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	18.870s	1.441ms	50	50	100.00
		hmac_long_msg	3.640m	3.872ms	50	50	100.00
		hmac_back_pressure	1.983m	3.933ms	50	50	100.00
		hmac_datapath_stress	28.350m	72.841ms	50	50	100.00
		hmac_burst_wr	1.523m	18.928ms	48	50	96.00
		hmac_error	3.817m	18.440ms	50	50	100.00
		hmac_wipe_secret	2.506m	65.215ms	50	50	100.00
		hmac_test_sha256_vectors	10.969m	103.954ms	5	5	100.00
		hmac_test_sha384_vectors	46.847m	844.610ms	5	5	100.00
		hmac_test_sha512_vectors	45.924m	1.550s	5	5	100.00
		hmac_test_hmac256_vectors	1.149m	6.635ms	5	5	100.00
		hmac_test_hmac384_vectors	1.653m	6.036ms	5	5	100.00
		hmac_test_hmac512_vectors	2.459m	35.274ms	5	5	100.00
		hmac_stress_all	1.570h	240.660ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.570h	240.660ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.630s	19.373us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	49.550us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.780s	1.005ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.780s	1.005ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.110s	36.558us	5	5	100.00
		hmac_csr_rw	1.020s	238.700us	20	20	100.00
		hmac_csr_aliasing	9.170s	2.396ms	5	5	100.00
		hmac_same_csr_outstanding	2.510s	316.283us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.110s	36.558us	5	5	100.00
		hmac_csr_rw	1.020s	238.700us	20	20	100.00
		hmac_csr_aliasing	9.170s	2.396ms	5	5	100.00
		hmac_same_csr_outstanding	2.510s	316.283us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	1.010s	822.275us	5	5	100.00
		hmac_tl_intg_err	4.510s	609.263us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.510s	609.263us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	18.870s	1.441ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.961h	414.541ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			657	660	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.45	95.40	97.17	100.00	100.00	98.27	98.48	99.85

Failure Buckets

UVM_ERROR (hmac_scoreboard.sv:483) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 3 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 3.hmac_stress_all_with_rand_reset.82225568262701365652016534586068952328612411358129595310662803218150991918417
    Line 56523, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5146379578 ps: (hmac_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 5146379578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_burst_wr has 2 failures.
  - 13.hmac_burst_wr.36262294703812038828431976626799725364029681044772641704860551620731664423496
    Line 300, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_burst_wr/latest/run.log
```
  UVM_ERROR @ 182179805 ps: (hmac_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 182179805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.hmac_burst_wr.55687789826503986057138277227009301570126491665562004212954213669247877519008
    Line 1346, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/30.hmac_burst_wr/latest/run.log
```
  UVM_ERROR @ 3171569449 ps: (hmac_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 3171569449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `39211701b5`