HMAC Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	15.540s	3.788ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.050s	44.873us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.000s	415.072us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.310s	1.062ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.700s	906.297us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	18.550m	499.040ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.000s	415.072us	20	20	100.00
		hmac_csr_aliasing	8.700s	906.297us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.577m	25.115ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.662m	8.373ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.898m	59.344ms	5	5	100.00
		hmac_test_sha384_vectors	44.436m	221.521ms	5	5	100.00
		hmac_test_sha512_vectors	40.188m	377.064ms	5	5	100.00
		hmac_test_hmac256_vectors	1.201m	6.643ms	5	5	100.00
		hmac_test_hmac384_vectors	1.863m	36.473ms	5	5	100.00
		hmac_test_hmac512_vectors	2.408m	52.920ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.425m	24.598ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	21.573m	6.781ms	50	50	100.00
V2	error	hmac_error	4.198m	20.647ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.283m	14.721ms	50	50	100.00
V2	save_and_restore	hmac_smoke	15.540s	3.788ms	50	50	100.00
		hmac_long_msg	3.577m	25.115ms	50	50	100.00
		hmac_back_pressure	1.662m	8.373ms	50	50	100.00
		hmac_datapath_stress	21.573m	6.781ms	50	50	100.00
		hmac_burst_wr	1.425m	24.598ms	49	50	98.00
		hmac_stress_all	54.802m	25.373ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	15.540s	3.788ms	50	50	100.00
		hmac_long_msg	3.577m	25.115ms	50	50	100.00
		hmac_back_pressure	1.662m	8.373ms	50	50	100.00
		hmac_datapath_stress	21.573m	6.781ms	50	50	100.00
		hmac_wipe_secret	2.283m	14.721ms	50	50	100.00
		hmac_test_sha256_vectors	11.898m	59.344ms	5	5	100.00
		hmac_test_sha384_vectors	44.436m	221.521ms	5	5	100.00
		hmac_test_sha512_vectors	40.188m	377.064ms	5	5	100.00
		hmac_test_hmac256_vectors	1.201m	6.643ms	5	5	100.00
		hmac_test_hmac384_vectors	1.863m	36.473ms	5	5	100.00
		hmac_test_hmac512_vectors	2.408m	52.920ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	15.540s	3.788ms	50	50	100.00
		hmac_long_msg	3.577m	25.115ms	50	50	100.00
		hmac_back_pressure	1.662m	8.373ms	50	50	100.00
		hmac_datapath_stress	21.573m	6.781ms	50	50	100.00
		hmac_burst_wr	1.425m	24.598ms	49	50	98.00
		hmac_error	4.198m	20.647ms	50	50	100.00
		hmac_wipe_secret	2.283m	14.721ms	50	50	100.00
		hmac_test_sha256_vectors	11.898m	59.344ms	5	5	100.00
		hmac_test_sha384_vectors	44.436m	221.521ms	5	5	100.00
		hmac_test_sha512_vectors	40.188m	377.064ms	5	5	100.00
		hmac_test_hmac256_vectors	1.201m	6.643ms	5	5	100.00
		hmac_test_hmac384_vectors	1.863m	36.473ms	5	5	100.00
		hmac_test_hmac512_vectors	2.408m	52.920ms	5	5	100.00
		hmac_stress_all	54.802m	25.373ms	50	50	100.00
V2	stress_all	hmac_stress_all	54.802m	25.373ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.660s	14.861us	50	50	100.00
V2	intr_test	hmac_intr_test	0.650s	68.909us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.240s	478.398us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.240s	478.398us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.050s	44.873us	5	5	100.00
		hmac_csr_rw	1.000s	415.072us	20	20	100.00
		hmac_csr_aliasing	8.700s	906.297us	5	5	100.00
		hmac_same_csr_outstanding	2.400s	305.253us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.050s	44.873us	5	5	100.00
		hmac_csr_rw	1.000s	415.072us	20	20	100.00
		hmac_csr_aliasing	8.700s	906.297us	5	5	100.00
		hmac_same_csr_outstanding	2.400s	305.253us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.070s	94.242us	5	5	100.00
		hmac_tl_intg_err	4.530s	233.614us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.530s	233.614us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	15.540s	3.788ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.450h	485.639ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			659	660	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	95.26	97.33	100.00	97.06	98.12	97.97	99.85

Failure Buckets

• UVM_ERROR (hmac_scoreboard.sv:483) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:
  • Test hmac_burst_wr has 1 failures.

    • 33.hmac_burst_wr.1523173503229672437531120689447104959001403173538103794506063115516179102486
      Line 1268, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/33.hmac_burst_wr/latest/run.log

        UVM_ERROR @ 13983770331 ps: (hmac_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 13983770331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.07.11_10.30.14
• 2024.07.10_10.37.00
• 2024.07.08_10.06.42
• 2024.07.07_10.30.13
• 2024.07.06_10.36.44
• 2024.07.05_11.01.44