HMAC Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.300s	974.530us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.020s	74.917us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.110s	142.368us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.800s	1.084ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.350s	162.774us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	3.376m	26.229ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.110s	142.368us	20	20	100.00
		hmac_csr_aliasing	8.350s	162.774us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.692m	22.222ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.703m	1.867ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.415m	72.362ms	5	5	100.00
		hmac_test_sha384_vectors	44.617m	444.068ms	5	5	100.00
		hmac_test_sha512_vectors	42.748m	144.929ms	5	5	100.00
		hmac_test_hmac256_vectors	1.328m	7.085ms	5	5	100.00
		hmac_test_hmac384_vectors	1.787m	28.359ms	5	5	100.00
		hmac_test_hmac512_vectors	1.859m	25.883ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.203m	11.967ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	35.547m	18.166ms	50	50	100.00
V2	error	hmac_error	4.266m	16.982ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.662m	12.371ms	50	50	100.00
V2	save_and_restore	hmac_smoke	17.300s	974.530us	50	50	100.00
		hmac_long_msg	3.692m	22.222ms	50	50	100.00
		hmac_back_pressure	1.703m	1.867ms	50	50	100.00
		hmac_datapath_stress	35.547m	18.166ms	50	50	100.00
		hmac_burst_wr	1.203m	11.967ms	50	50	100.00
		hmac_stress_all	1.627h	468.484ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.300s	974.530us	50	50	100.00
		hmac_long_msg	3.692m	22.222ms	50	50	100.00
		hmac_back_pressure	1.703m	1.867ms	50	50	100.00
		hmac_datapath_stress	35.547m	18.166ms	50	50	100.00
		hmac_wipe_secret	2.662m	12.371ms	50	50	100.00
		hmac_test_sha256_vectors	11.415m	72.362ms	5	5	100.00
		hmac_test_sha384_vectors	44.617m	444.068ms	5	5	100.00
		hmac_test_sha512_vectors	42.748m	144.929ms	5	5	100.00
		hmac_test_hmac256_vectors	1.328m	7.085ms	5	5	100.00
		hmac_test_hmac384_vectors	1.787m	28.359ms	5	5	100.00
		hmac_test_hmac512_vectors	1.859m	25.883ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.300s	974.530us	50	50	100.00
		hmac_long_msg	3.692m	22.222ms	50	50	100.00
		hmac_back_pressure	1.703m	1.867ms	50	50	100.00
		hmac_datapath_stress	35.547m	18.166ms	50	50	100.00
		hmac_burst_wr	1.203m	11.967ms	50	50	100.00
		hmac_error	4.266m	16.982ms	50	50	100.00
		hmac_wipe_secret	2.662m	12.371ms	50	50	100.00
		hmac_test_sha256_vectors	11.415m	72.362ms	5	5	100.00
		hmac_test_sha384_vectors	44.617m	444.068ms	5	5	100.00
		hmac_test_sha512_vectors	42.748m	144.929ms	5	5	100.00
		hmac_test_hmac256_vectors	1.328m	7.085ms	5	5	100.00
		hmac_test_hmac384_vectors	1.787m	28.359ms	5	5	100.00
		hmac_test_hmac512_vectors	1.859m	25.883ms	5	5	100.00
		hmac_stress_all	1.627h	468.484ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.627h	468.484ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.630s	12.995us	50	50	100.00
V2	intr_test	hmac_intr_test	0.650s	55.845us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.290s	506.173us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.290s	506.173us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.020s	74.917us	5	5	100.00
		hmac_csr_rw	1.110s	142.368us	20	20	100.00
		hmac_csr_aliasing	8.350s	162.774us	5	5	100.00
		hmac_same_csr_outstanding	2.420s	163.098us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.020s	74.917us	5	5	100.00
		hmac_csr_rw	1.110s	142.368us	20	20	100.00
		hmac_csr_aliasing	8.350s	162.774us	5	5	100.00
		hmac_same_csr_outstanding	2.420s	163.098us	20	20	100.00
V2		TOTAL			520	520	100.00
V2S	tl_intg_err	hmac_sec_cm	1.050s	178.094us	5	5	100.00
		hmac_tl_intg_err	4.690s	1.579ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.690s	1.579ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.300s	974.530us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.225h	96.076ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			658	660	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.34	95.26	97.17	100.00	100.00	98.12	97.97	99.85

Failure Buckets

• UVM_ERROR (hmac_scoreboard.sv:483) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 3.hmac_stress_all_with_rand_reset.3542223885386778776241654903746830395173722283405391073640413107342450241221
      Line 276724, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 56549790282 ps: (hmac_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 56549790282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job hmac-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 5.hmac_stress_all_with_rand_reset.38481494520924530710160947947484035400643196411100665840100227718883160625082
      Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:d1249be6-8baa-4694-9006-ba5963b4daa3
      

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