HMAC Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 17.750s 2.725ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.020s 128.789us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.960s 136.791us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.040s 1.464ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 6.370s 2.054ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 16.380m 104.204ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.960s 136.791us 20 20 100.00
hmac_csr_aliasing 6.370s 2.054ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 3.791m 47.484ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.935m 9.741ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 10.489m 11.193ms 5 5 100.00
hmac_test_sha384_vectors 42.498m 183.208ms 5 5 100.00
hmac_test_sha512_vectors 47.363m 893.811ms 5 5 100.00
hmac_test_hmac256_vectors 1.253m 16.957ms 5 5 100.00
hmac_test_hmac384_vectors 1.648m 2.399ms 5 5 100.00
hmac_test_hmac512_vectors 1.937m 31.784ms 5 5 100.00
V2 burst_wr hmac_burst_wr 1.462m 26.993ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 31.788m 9.603ms 50 50 100.00
V2 error hmac_error 4.105m 56.144ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.345m 60.147ms 50 50 100.00
V2 save_and_restore hmac_smoke 17.750s 2.725ms 50 50 100.00
hmac_long_msg 3.791m 47.484ms 50 50 100.00
hmac_back_pressure 1.935m 9.741ms 50 50 100.00
hmac_datapath_stress 31.788m 9.603ms 50 50 100.00
hmac_burst_wr 1.462m 26.993ms 50 50 100.00
hmac_stress_all 1.463h 36.269ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 17.750s 2.725ms 50 50 100.00
hmac_long_msg 3.791m 47.484ms 50 50 100.00
hmac_back_pressure 1.935m 9.741ms 50 50 100.00
hmac_datapath_stress 31.788m 9.603ms 50 50 100.00
hmac_wipe_secret 2.345m 60.147ms 50 50 100.00
hmac_test_sha256_vectors 10.489m 11.193ms 5 5 100.00
hmac_test_sha384_vectors 42.498m 183.208ms 5 5 100.00
hmac_test_sha512_vectors 47.363m 893.811ms 5 5 100.00
hmac_test_hmac256_vectors 1.253m 16.957ms 5 5 100.00
hmac_test_hmac384_vectors 1.648m 2.399ms 5 5 100.00
hmac_test_hmac512_vectors 1.937m 31.784ms 5 5 100.00
V2 wide_digest_configurable_key_length hmac_smoke 17.750s 2.725ms 50 50 100.00
hmac_long_msg 3.791m 47.484ms 50 50 100.00
hmac_back_pressure 1.935m 9.741ms 50 50 100.00
hmac_datapath_stress 31.788m 9.603ms 50 50 100.00
hmac_burst_wr 1.462m 26.993ms 50 50 100.00
hmac_error 4.105m 56.144ms 50 50 100.00
hmac_wipe_secret 2.345m 60.147ms 50 50 100.00
hmac_test_sha256_vectors 10.489m 11.193ms 5 5 100.00
hmac_test_sha384_vectors 42.498m 183.208ms 5 5 100.00
hmac_test_sha512_vectors 47.363m 893.811ms 5 5 100.00
hmac_test_hmac256_vectors 1.253m 16.957ms 5 5 100.00
hmac_test_hmac384_vectors 1.648m 2.399ms 5 5 100.00
hmac_test_hmac512_vectors 1.937m 31.784ms 5 5 100.00
hmac_stress_all 1.463h 36.269ms 50 50 100.00
V2 stress_all hmac_stress_all 1.463h 36.269ms 50 50 100.00
V2 alert_test hmac_alert_test 0.650s 12.778us 50 50 100.00
V2 intr_test hmac_intr_test 0.700s 20.636us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.950s 187.098us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.950s 187.098us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.020s 128.789us 5 5 100.00
hmac_csr_rw 0.960s 136.791us 20 20 100.00
hmac_csr_aliasing 6.370s 2.054ms 5 5 100.00
hmac_same_csr_outstanding 2.330s 116.910us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.020s 128.789us 5 5 100.00
hmac_csr_rw 0.960s 136.791us 20 20 100.00
hmac_csr_aliasing 6.370s 2.054ms 5 5 100.00
hmac_same_csr_outstanding 2.330s 116.910us 20 20 100.00
V2 TOTAL 520 520 100.00
V2S tl_intg_err hmac_sec_cm 1.010s 85.685us 5 5 100.00
hmac_tl_intg_err 4.440s 567.429us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.440s 567.429us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 17.750s 2.725ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.371h 192.674ms 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 660 660 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.61 95.40 97.17 100.00 94.12 98.27 98.48 99.85

Past Results