HMAC Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	18.650s	5.903ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.060s	41.932us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.970s	39.755us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.730s	1.646ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.560s	532.251us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	18.404m	181.500ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.970s	39.755us	20	20	100.00
		hmac_csr_aliasing	8.560s	532.251us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.106m	200.000ms	49	50	98.00
V2	back_pressure	hmac_back_pressure	1.926m	7.276ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	12.592m	60.560ms	5	5	100.00
		hmac_test_sha384_vectors	43.925m	422.133ms	5	5	100.00
		hmac_test_sha512_vectors	42.370m	211.440ms	5	5	100.00
		hmac_test_hmac256_vectors	1.215m	1.880ms	5	5	100.00
		hmac_test_hmac384_vectors	1.910m	18.238ms	5	5	100.00
		hmac_test_hmac512_vectors	2.097m	15.898ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.289m	4.379ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	25.255m	10.842ms	50	50	100.00
V2	error	hmac_error	4.127m	38.456ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.365m	11.089ms	50	50	100.00
V2	save_and_restore	hmac_smoke	18.650s	5.903ms	50	50	100.00
		hmac_long_msg	4.106m	200.000ms	49	50	98.00
		hmac_back_pressure	1.926m	7.276ms	50	50	100.00
		hmac_datapath_stress	25.255m	10.842ms	50	50	100.00
		hmac_burst_wr	1.289m	4.379ms	49	50	98.00
		hmac_stress_all	1.318h	164.142ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	18.650s	5.903ms	50	50	100.00
		hmac_long_msg	4.106m	200.000ms	49	50	98.00
		hmac_back_pressure	1.926m	7.276ms	50	50	100.00
		hmac_datapath_stress	25.255m	10.842ms	50	50	100.00
		hmac_wipe_secret	2.365m	11.089ms	50	50	100.00
		hmac_test_sha256_vectors	12.592m	60.560ms	5	5	100.00
		hmac_test_sha384_vectors	43.925m	422.133ms	5	5	100.00
		hmac_test_sha512_vectors	42.370m	211.440ms	5	5	100.00
		hmac_test_hmac256_vectors	1.215m	1.880ms	5	5	100.00
		hmac_test_hmac384_vectors	1.910m	18.238ms	5	5	100.00
		hmac_test_hmac512_vectors	2.097m	15.898ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	18.650s	5.903ms	50	50	100.00
		hmac_long_msg	4.106m	200.000ms	49	50	98.00
		hmac_back_pressure	1.926m	7.276ms	50	50	100.00
		hmac_datapath_stress	25.255m	10.842ms	50	50	100.00
		hmac_burst_wr	1.289m	4.379ms	49	50	98.00
		hmac_error	4.127m	38.456ms	50	50	100.00
		hmac_wipe_secret	2.365m	11.089ms	50	50	100.00
		hmac_test_sha256_vectors	12.592m	60.560ms	5	5	100.00
		hmac_test_sha384_vectors	43.925m	422.133ms	5	5	100.00
		hmac_test_sha512_vectors	42.370m	211.440ms	5	5	100.00
		hmac_test_hmac256_vectors	1.215m	1.880ms	5	5	100.00
		hmac_test_hmac384_vectors	1.910m	18.238ms	5	5	100.00
		hmac_test_hmac512_vectors	2.097m	15.898ms	5	5	100.00
		hmac_stress_all	1.318h	164.142ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.318h	164.142ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.660s	28.346us	50	50	100.00
V2	intr_test	hmac_intr_test	0.700s	15.729us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.500s	240.711us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.500s	240.711us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.060s	41.932us	5	5	100.00
		hmac_csr_rw	0.970s	39.755us	20	20	100.00
		hmac_csr_aliasing	8.560s	532.251us	5	5	100.00
		hmac_same_csr_outstanding	2.540s	311.098us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.060s	41.932us	5	5	100.00
		hmac_csr_rw	0.970s	39.755us	20	20	100.00
		hmac_csr_aliasing	8.560s	532.251us	5	5	100.00
		hmac_same_csr_outstanding	2.540s	311.098us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	0.960s	84.897us	5	5	100.00
		hmac_tl_intg_err	4.560s	435.475us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.560s	435.475us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	18.650s	5.903ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.348h	256.351ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			658	660	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.03	95.40	97.17	100.00	97.06	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_scoreboard.sv:483) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:

  • Test hmac_burst_wr has 1 failures.

    • 12.hmac_burst_wr.68018018985824418042131182728788034041072284324714676791041139629364629956775
      Line 334, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/12.hmac_burst_wr/latest/run.log

        UVM_ERROR @ 448829931 ps: (hmac_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 448829931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test hmac_long_msg has 1 failures.

    • 36.hmac_long_msg.95737196411941622576348996724414461618138861509479420566217419551418156801500
      Line 42351, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/36.hmac_long_msg/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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