HMAC Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.330s	1.334ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.070s	152.875us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.980s	56.282us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.790s	1.668ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.360s	156.743us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	19.290m	413.013ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.980s	56.282us	20	20	100.00
		hmac_csr_aliasing	8.360s	156.743us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.615m	45.054ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.834m	7.054ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.960m	238.027ms	4	5	80.00
		hmac_test_sha384_vectors	41.422m	2.748s	5	5	100.00
		hmac_test_sha512_vectors	43.410m	2.924s	5	5	100.00
		hmac_test_hmac256_vectors	1.326m	13.088ms	5	5	100.00
		hmac_test_hmac384_vectors	1.831m	107.466ms	5	5	100.00
		hmac_test_hmac512_vectors	2.325m	50.435ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.119m	10.541ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	32.872m	8.733ms	50	50	100.00
V2	error	hmac_error	3.683m	25.884ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.224m	17.427ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.330s	1.334ms	50	50	100.00
		hmac_long_msg	3.615m	45.054ms	50	50	100.00
		hmac_back_pressure	1.834m	7.054ms	50	50	100.00
		hmac_datapath_stress	32.872m	8.733ms	50	50	100.00
		hmac_burst_wr	1.119m	10.541ms	50	50	100.00
		hmac_stress_all	1.409h	235.245ms	49	50	98.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.330s	1.334ms	50	50	100.00
		hmac_long_msg	3.615m	45.054ms	50	50	100.00
		hmac_back_pressure	1.834m	7.054ms	50	50	100.00
		hmac_datapath_stress	32.872m	8.733ms	50	50	100.00
		hmac_wipe_secret	2.224m	17.427ms	50	50	100.00
		hmac_test_sha256_vectors	10.960m	238.027ms	4	5	80.00
		hmac_test_sha384_vectors	41.422m	2.748s	5	5	100.00
		hmac_test_sha512_vectors	43.410m	2.924s	5	5	100.00
		hmac_test_hmac256_vectors	1.326m	13.088ms	5	5	100.00
		hmac_test_hmac384_vectors	1.831m	107.466ms	5	5	100.00
		hmac_test_hmac512_vectors	2.325m	50.435ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.330s	1.334ms	50	50	100.00
		hmac_long_msg	3.615m	45.054ms	50	50	100.00
		hmac_back_pressure	1.834m	7.054ms	50	50	100.00
		hmac_datapath_stress	32.872m	8.733ms	50	50	100.00
		hmac_burst_wr	1.119m	10.541ms	50	50	100.00
		hmac_error	3.683m	25.884ms	50	50	100.00
		hmac_wipe_secret	2.224m	17.427ms	50	50	100.00
		hmac_test_sha256_vectors	10.960m	238.027ms	4	5	80.00
		hmac_test_sha384_vectors	41.422m	2.748s	5	5	100.00
		hmac_test_sha512_vectors	43.410m	2.924s	5	5	100.00
		hmac_test_hmac256_vectors	1.326m	13.088ms	5	5	100.00
		hmac_test_hmac384_vectors	1.831m	107.466ms	5	5	100.00
		hmac_test_hmac512_vectors	2.325m	50.435ms	5	5	100.00
		hmac_stress_all	1.409h	235.245ms	49	50	98.00
V2	stress_all	hmac_stress_all	1.409h	235.245ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.640s	13.909us	50	50	100.00
V2	intr_test	hmac_intr_test	0.660s	35.957us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.370s	158.762us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.370s	158.762us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.070s	152.875us	5	5	100.00
		hmac_csr_rw	0.980s	56.282us	20	20	100.00
		hmac_csr_aliasing	8.360s	156.743us	5	5	100.00
		hmac_same_csr_outstanding	2.440s	485.473us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.070s	152.875us	5	5	100.00
		hmac_csr_rw	0.980s	56.282us	20	20	100.00
		hmac_csr_aliasing	8.360s	156.743us	5	5	100.00
		hmac_same_csr_outstanding	2.440s	485.473us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	1.030s	348.939us	5	5	100.00
		hmac_tl_intg_err	4.550s	334.344us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.550s	334.344us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.330s	1.334ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.368h	147.230ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			658	660	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.35	95.26	97.22	100.00	100.00	98.12	97.97	99.85

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test hmac_test_sha256_vectors has 1 failures.

    • 2.hmac_test_sha256_vectors.84870234171137763527573122446343588732832541123400944661405603652434824672246
      Line 66939, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest/run.log

        UVM_FATAL @ 800000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 800000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 800000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_scoreboard.sv:483) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:

  • Test hmac_stress_all has 1 failures.

    • 35.hmac_stress_all.106733920865579963784586271908992114272472948683661998551746324898493552643821
      Line 36182, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/35.hmac_stress_all/latest/run.log

        UVM_ERROR @ 4265059697 ps: (hmac_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 4265059697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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