HMAC Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.230s	5.103ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.960s	20.223us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.000s	38.889us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	17.850s	10.466ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.880s	446.969us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	16.820m	102.989ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.000s	38.889us	20	20	100.00
		hmac_csr_aliasing	8.880s	446.969us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.977m	12.713ms	49	50	98.00
V2	back_pressure	hmac_back_pressure	1.888m	1.854ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.296m	57.110ms	5	5	100.00
		hmac_test_sha384_vectors	43.288m	202.876ms	5	5	100.00
		hmac_test_sha512_vectors	43.326m	229.407ms	5	5	100.00
		hmac_test_hmac256_vectors	1.369m	4.895ms	5	5	100.00
		hmac_test_hmac384_vectors	1.465m	2.239ms	5	5	100.00
		hmac_test_hmac512_vectors	2.076m	43.538ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.293m	5.673ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	26.060m	8.008ms	50	50	100.00
V2	error	hmac_error	3.429m	3.635ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.304m	7.876ms	50	50	100.00
V2	save_and_restore	hmac_smoke	17.230s	5.103ms	50	50	100.00
		hmac_long_msg	3.977m	12.713ms	49	50	98.00
		hmac_back_pressure	1.888m	1.854ms	50	50	100.00
		hmac_datapath_stress	26.060m	8.008ms	50	50	100.00
		hmac_burst_wr	1.293m	5.673ms	50	50	100.00
		hmac_stress_all	1.344h	138.198ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.230s	5.103ms	50	50	100.00
		hmac_long_msg	3.977m	12.713ms	49	50	98.00
		hmac_back_pressure	1.888m	1.854ms	50	50	100.00
		hmac_datapath_stress	26.060m	8.008ms	50	50	100.00
		hmac_wipe_secret	2.304m	7.876ms	50	50	100.00
		hmac_test_sha256_vectors	11.296m	57.110ms	5	5	100.00
		hmac_test_sha384_vectors	43.288m	202.876ms	5	5	100.00
		hmac_test_sha512_vectors	43.326m	229.407ms	5	5	100.00
		hmac_test_hmac256_vectors	1.369m	4.895ms	5	5	100.00
		hmac_test_hmac384_vectors	1.465m	2.239ms	5	5	100.00
		hmac_test_hmac512_vectors	2.076m	43.538ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.230s	5.103ms	50	50	100.00
		hmac_long_msg	3.977m	12.713ms	49	50	98.00
		hmac_back_pressure	1.888m	1.854ms	50	50	100.00
		hmac_datapath_stress	26.060m	8.008ms	50	50	100.00
		hmac_burst_wr	1.293m	5.673ms	50	50	100.00
		hmac_error	3.429m	3.635ms	50	50	100.00
		hmac_wipe_secret	2.304m	7.876ms	50	50	100.00
		hmac_test_sha256_vectors	11.296m	57.110ms	5	5	100.00
		hmac_test_sha384_vectors	43.288m	202.876ms	5	5	100.00
		hmac_test_sha512_vectors	43.326m	229.407ms	5	5	100.00
		hmac_test_hmac256_vectors	1.369m	4.895ms	5	5	100.00
		hmac_test_hmac384_vectors	1.465m	2.239ms	5	5	100.00
		hmac_test_hmac512_vectors	2.076m	43.538ms	5	5	100.00
		hmac_stress_all	1.344h	138.198ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.344h	138.198ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.660s	32.800us	50	50	100.00
V2	intr_test	hmac_intr_test	0.660s	106.327us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.420s	260.340us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.420s	260.340us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.960s	20.223us	5	5	100.00
		hmac_csr_rw	1.000s	38.889us	20	20	100.00
		hmac_csr_aliasing	8.880s	446.969us	5	5	100.00
		hmac_same_csr_outstanding	2.490s	149.993us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.960s	20.223us	5	5	100.00
		hmac_csr_rw	1.000s	38.889us	20	20	100.00
		hmac_csr_aliasing	8.880s	446.969us	5	5	100.00
		hmac_same_csr_outstanding	2.490s	149.993us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.000s	106.330us	5	5	100.00
		hmac_tl_intg_err	4.500s	279.925us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.500s	279.925us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.230s	5.103ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.120h	113.545ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			659	660	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.04	95.40	97.22	100.00	97.06	98.27	98.48	99.85

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test hmac_long_msg has 1 failures.

    • 1.hmac_long_msg.52833379659677355649130853717326735330638488398684460696260935599564750696753
      Line 23865, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_long_msg/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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