HMAC Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.510s	2.228ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.070s	578.744us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.070s	180.240us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.720s	2.226ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.090s	2.678ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	21.868m	261.926ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.070s	180.240us	20	20	100.00
		hmac_csr_aliasing	6.090s	2.678ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.965m	56.550ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.778m	1.663ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.480m	51.905ms	5	5	100.00
		hmac_test_sha384_vectors	42.227m	139.304ms	5	5	100.00
		hmac_test_sha512_vectors	40.878m	274.909ms	5	5	100.00
		hmac_test_hmac256_vectors	1.241m	9.034ms	5	5	100.00
		hmac_test_hmac384_vectors	1.898m	27.045ms	5	5	100.00
		hmac_test_hmac512_vectors	2.325m	8.746ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.422m	1.451ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	27.992m	41.882ms	50	50	100.00
V2	error	hmac_error	3.912m	51.393ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.477m	42.544ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.510s	2.228ms	50	50	100.00
		hmac_long_msg	3.965m	56.550ms	50	50	100.00
		hmac_back_pressure	1.778m	1.663ms	50	50	100.00
		hmac_datapath_stress	27.992m	41.882ms	50	50	100.00
		hmac_burst_wr	1.422m	1.451ms	49	50	98.00
		hmac_stress_all	1.150h	326.360ms	49	50	98.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.510s	2.228ms	50	50	100.00
		hmac_long_msg	3.965m	56.550ms	50	50	100.00
		hmac_back_pressure	1.778m	1.663ms	50	50	100.00
		hmac_datapath_stress	27.992m	41.882ms	50	50	100.00
		hmac_wipe_secret	2.477m	42.544ms	50	50	100.00
		hmac_test_sha256_vectors	11.480m	51.905ms	5	5	100.00
		hmac_test_sha384_vectors	42.227m	139.304ms	5	5	100.00
		hmac_test_sha512_vectors	40.878m	274.909ms	5	5	100.00
		hmac_test_hmac256_vectors	1.241m	9.034ms	5	5	100.00
		hmac_test_hmac384_vectors	1.898m	27.045ms	5	5	100.00
		hmac_test_hmac512_vectors	2.325m	8.746ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.510s	2.228ms	50	50	100.00
		hmac_long_msg	3.965m	56.550ms	50	50	100.00
		hmac_back_pressure	1.778m	1.663ms	50	50	100.00
		hmac_datapath_stress	27.992m	41.882ms	50	50	100.00
		hmac_burst_wr	1.422m	1.451ms	49	50	98.00
		hmac_error	3.912m	51.393ms	50	50	100.00
		hmac_wipe_secret	2.477m	42.544ms	50	50	100.00
		hmac_test_sha256_vectors	11.480m	51.905ms	5	5	100.00
		hmac_test_sha384_vectors	42.227m	139.304ms	5	5	100.00
		hmac_test_sha512_vectors	40.878m	274.909ms	5	5	100.00
		hmac_test_hmac256_vectors	1.241m	9.034ms	5	5	100.00
		hmac_test_hmac384_vectors	1.898m	27.045ms	5	5	100.00
		hmac_test_hmac512_vectors	2.325m	8.746ms	5	5	100.00
		hmac_stress_all	1.150h	326.360ms	49	50	98.00
V2	stress_all	hmac_stress_all	1.150h	326.360ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.660s	16.236us	50	50	100.00
V2	intr_test	hmac_intr_test	0.690s	30.452us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.870s	155.193us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.870s	155.193us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.070s	578.744us	5	5	100.00
		hmac_csr_rw	1.070s	180.240us	20	20	100.00
		hmac_csr_aliasing	6.090s	2.678ms	5	5	100.00
		hmac_same_csr_outstanding	2.700s	687.653us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.070s	578.744us	5	5	100.00
		hmac_csr_rw	1.070s	180.240us	20	20	100.00
		hmac_csr_aliasing	6.090s	2.678ms	5	5	100.00
		hmac_same_csr_outstanding	2.700s	687.653us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	1.030s	82.538us	5	5	100.00
		hmac_tl_intg_err	4.480s	1.764ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.480s	1.764ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.510s	2.228ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.766h	118.033ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			657	660	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.03	95.40	97.17	100.00	97.06	98.27	98.48	99.85

Failure Buckets

UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 3 failures:
- Test hmac_burst_wr has 1 failures.
  - 3.hmac_burst_wr.71983265048862180419257243339236807898564922020138696765025374276842926654074
    Line 1331, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_burst_wr/latest/run.log
```
  UVM_ERROR @ 1917672088 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 1917672088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 7.hmac_stress_all_with_rand_reset.6612760112101241801941696888554655460289207933516407081581714995344450062355
    Line 104598, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 55049395586 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 55049395586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_stress_all has 1 failures.
  - 29.hmac_stress_all.82748705766269576542505450534722000610557063213442175283957789332947460505035
    Line 57267, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/29.hmac_stress_all/latest/run.log
```
  UVM_ERROR @ 14710474434 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 14710474434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8b2da8db5e`