HMAC Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	18.560s	1.539ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.970s	81.760us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.010s	154.648us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.390s	390.226us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.510s	2.955ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	16.021m	90.265ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.010s	154.648us	20	20	100.00
		hmac_csr_aliasing	8.510s	2.955ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.029m	71.023ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.827m	10.109ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.310m	11.127ms	5	5	100.00
		hmac_test_sha384_vectors	45.574m	218.760ms	5	5	100.00
		hmac_test_sha512_vectors	45.095m	1.430s	5	5	100.00
		hmac_test_hmac256_vectors	1.373m	17.406ms	5	5	100.00
		hmac_test_hmac384_vectors	1.867m	19.429ms	5	5	100.00
		hmac_test_hmac512_vectors	2.275m	17.240ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.308m	5.934ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	27.011m	16.911ms	50	50	100.00
V2	error	hmac_error	5.039m	90.615ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.262m	48.939ms	50	50	100.00
V2	save_and_restore	hmac_smoke	18.560s	1.539ms	50	50	100.00
		hmac_long_msg	4.029m	71.023ms	50	50	100.00
		hmac_back_pressure	1.827m	10.109ms	50	50	100.00
		hmac_datapath_stress	27.011m	16.911ms	50	50	100.00
		hmac_burst_wr	1.308m	5.934ms	50	50	100.00
		hmac_stress_all	1.158h	180.477ms	49	50	98.00
V2	fifo_empty_status_interrupt	hmac_smoke	18.560s	1.539ms	50	50	100.00
		hmac_long_msg	4.029m	71.023ms	50	50	100.00
		hmac_back_pressure	1.827m	10.109ms	50	50	100.00
		hmac_datapath_stress	27.011m	16.911ms	50	50	100.00
		hmac_wipe_secret	2.262m	48.939ms	50	50	100.00
		hmac_test_sha256_vectors	10.310m	11.127ms	5	5	100.00
		hmac_test_sha384_vectors	45.574m	218.760ms	5	5	100.00
		hmac_test_sha512_vectors	45.095m	1.430s	5	5	100.00
		hmac_test_hmac256_vectors	1.373m	17.406ms	5	5	100.00
		hmac_test_hmac384_vectors	1.867m	19.429ms	5	5	100.00
		hmac_test_hmac512_vectors	2.275m	17.240ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	18.560s	1.539ms	50	50	100.00
		hmac_long_msg	4.029m	71.023ms	50	50	100.00
		hmac_back_pressure	1.827m	10.109ms	50	50	100.00
		hmac_datapath_stress	27.011m	16.911ms	50	50	100.00
		hmac_burst_wr	1.308m	5.934ms	50	50	100.00
		hmac_error	5.039m	90.615ms	50	50	100.00
		hmac_wipe_secret	2.262m	48.939ms	50	50	100.00
		hmac_test_sha256_vectors	10.310m	11.127ms	5	5	100.00
		hmac_test_sha384_vectors	45.574m	218.760ms	5	5	100.00
		hmac_test_sha512_vectors	45.095m	1.430s	5	5	100.00
		hmac_test_hmac256_vectors	1.373m	17.406ms	5	5	100.00
		hmac_test_hmac384_vectors	1.867m	19.429ms	5	5	100.00
		hmac_test_hmac512_vectors	2.275m	17.240ms	5	5	100.00
		hmac_stress_all	1.158h	180.477ms	49	50	98.00
V2	stress_all	hmac_stress_all	1.158h	180.477ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.660s	69.648us	50	50	100.00
V2	intr_test	hmac_intr_test	0.650s	30.604us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.730s	1.208ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.730s	1.208ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.970s	81.760us	5	5	100.00
		hmac_csr_rw	1.010s	154.648us	20	20	100.00
		hmac_csr_aliasing	8.510s	2.955ms	5	5	100.00
		hmac_same_csr_outstanding	2.410s	157.152us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.970s	81.760us	5	5	100.00
		hmac_csr_rw	1.010s	154.648us	20	20	100.00
		hmac_csr_aliasing	8.510s	2.955ms	5	5	100.00
		hmac_same_csr_outstanding	2.410s	157.152us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.160s	565.107us	5	5	100.00
		hmac_tl_intg_err	4.410s	970.565us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.410s	970.565us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	18.560s	1.539ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.954h	1.438s	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			659	660	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.04	95.40	97.22	100.00	97.06	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:
  • Test hmac_stress_all has 1 failures.

    • 44.hmac_stress_all.109515191966286821063788834528237043878961556285042860742353686848269503998145
      Line 58264, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/44.hmac_stress_all/latest/run.log

        UVM_ERROR @ 6667183422 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 6667183422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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