HMAC Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.410s	5.625ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.010s	463.706us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.960s	30.758us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	10.910s	1.833ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	5.870s	354.364us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	30.997m	436.393ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.960s	30.758us	20	20	100.00
		hmac_csr_aliasing	5.870s	354.364us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.075m	17.209ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.737m	3.541ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.056m	143.888ms	5	5	100.00
		hmac_test_sha384_vectors	45.632m	221.980ms	5	5	100.00
		hmac_test_sha512_vectors	47.102m	558.832ms	5	5	100.00
		hmac_test_hmac256_vectors	1.317m	6.130ms	5	5	100.00
		hmac_test_hmac384_vectors	1.788m	6.832ms	5	5	100.00
		hmac_test_hmac512_vectors	2.248m	34.746ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.314m	5.547ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	30.948m	16.612ms	50	50	100.00
V2	error	hmac_error	3.875m	15.376ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.398m	10.629ms	50	50	100.00
V2	save_and_restore	hmac_smoke	17.410s	5.625ms	50	50	100.00
		hmac_long_msg	4.075m	17.209ms	50	50	100.00
		hmac_back_pressure	1.737m	3.541ms	50	50	100.00
		hmac_datapath_stress	30.948m	16.612ms	50	50	100.00
		hmac_burst_wr	1.314m	5.547ms	49	50	98.00
		hmac_stress_all	55.737m	96.198ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.410s	5.625ms	50	50	100.00
		hmac_long_msg	4.075m	17.209ms	50	50	100.00
		hmac_back_pressure	1.737m	3.541ms	50	50	100.00
		hmac_datapath_stress	30.948m	16.612ms	50	50	100.00
		hmac_wipe_secret	2.398m	10.629ms	50	50	100.00
		hmac_test_sha256_vectors	11.056m	143.888ms	5	5	100.00
		hmac_test_sha384_vectors	45.632m	221.980ms	5	5	100.00
		hmac_test_sha512_vectors	47.102m	558.832ms	5	5	100.00
		hmac_test_hmac256_vectors	1.317m	6.130ms	5	5	100.00
		hmac_test_hmac384_vectors	1.788m	6.832ms	5	5	100.00
		hmac_test_hmac512_vectors	2.248m	34.746ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.410s	5.625ms	50	50	100.00
		hmac_long_msg	4.075m	17.209ms	50	50	100.00
		hmac_back_pressure	1.737m	3.541ms	50	50	100.00
		hmac_datapath_stress	30.948m	16.612ms	50	50	100.00
		hmac_burst_wr	1.314m	5.547ms	49	50	98.00
		hmac_error	3.875m	15.376ms	50	50	100.00
		hmac_wipe_secret	2.398m	10.629ms	50	50	100.00
		hmac_test_sha256_vectors	11.056m	143.888ms	5	5	100.00
		hmac_test_sha384_vectors	45.632m	221.980ms	5	5	100.00
		hmac_test_sha512_vectors	47.102m	558.832ms	5	5	100.00
		hmac_test_hmac256_vectors	1.317m	6.130ms	5	5	100.00
		hmac_test_hmac384_vectors	1.788m	6.832ms	5	5	100.00
		hmac_test_hmac512_vectors	2.248m	34.746ms	5	5	100.00
		hmac_stress_all	55.737m	96.198ms	50	50	100.00
V2	stress_all	hmac_stress_all	55.737m	96.198ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.670s	20.342us	50	50	100.00
V2	intr_test	hmac_intr_test	0.670s	77.740us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.420s	1.022ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.420s	1.022ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.010s	463.706us	5	5	100.00
		hmac_csr_rw	0.960s	30.758us	20	20	100.00
		hmac_csr_aliasing	5.870s	354.364us	5	5	100.00
		hmac_same_csr_outstanding	2.470s	558.730us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.010s	463.706us	5	5	100.00
		hmac_csr_rw	0.960s	30.758us	20	20	100.00
		hmac_csr_aliasing	5.870s	354.364us	5	5	100.00
		hmac_same_csr_outstanding	2.470s	558.730us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.200s	126.061us	5	5	100.00
		hmac_tl_intg_err	4.300s	1.020ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.300s	1.020ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.410s	5.625ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.016h	320.765ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			659	660	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.04	95.40	97.22	100.00	97.06	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:
  • Test hmac_burst_wr has 1 failures.

    • 7.hmac_burst_wr.29519275934057530610849359312646970440914683917250325929912110595067298079444
      Line 1112, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_burst_wr/latest/run.log

        UVM_ERROR @ 5814371618 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 5814371618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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