HMAC Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.050s	2.766ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.020s	182.516us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.020s	20.598us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.730s	1.221ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.710s	555.476us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	11.180m	68.616ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.020s	20.598us	20	20	100.00
		hmac_csr_aliasing	8.710s	555.476us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.927m	40.188ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.027m	4.019ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.583m	164.703ms	5	5	100.00
		hmac_test_sha384_vectors	41.599m	240.634ms	5	5	100.00
		hmac_test_sha512_vectors	43.563m	885.358ms	5	5	100.00
		hmac_test_hmac256_vectors	1.199m	12.344ms	5	5	100.00
		hmac_test_hmac384_vectors	1.480m	5.596ms	5	5	100.00
		hmac_test_hmac512_vectors	2.181m	7.627ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.159m	3.808ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	23.186m	7.289ms	50	50	100.00
V2	error	hmac_error	4.370m	245.759ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.206m	12.169ms	50	50	100.00
V2	save_and_restore	hmac_smoke	17.050s	2.766ms	50	50	100.00
		hmac_long_msg	2.927m	40.188ms	50	50	100.00
		hmac_back_pressure	2.027m	4.019ms	50	50	100.00
		hmac_datapath_stress	23.186m	7.289ms	50	50	100.00
		hmac_burst_wr	1.159m	3.808ms	49	50	98.00
		hmac_stress_all	45.706m	78.863ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.050s	2.766ms	50	50	100.00
		hmac_long_msg	2.927m	40.188ms	50	50	100.00
		hmac_back_pressure	2.027m	4.019ms	50	50	100.00
		hmac_datapath_stress	23.186m	7.289ms	50	50	100.00
		hmac_wipe_secret	2.206m	12.169ms	50	50	100.00
		hmac_test_sha256_vectors	11.583m	164.703ms	5	5	100.00
		hmac_test_sha384_vectors	41.599m	240.634ms	5	5	100.00
		hmac_test_sha512_vectors	43.563m	885.358ms	5	5	100.00
		hmac_test_hmac256_vectors	1.199m	12.344ms	5	5	100.00
		hmac_test_hmac384_vectors	1.480m	5.596ms	5	5	100.00
		hmac_test_hmac512_vectors	2.181m	7.627ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.050s	2.766ms	50	50	100.00
		hmac_long_msg	2.927m	40.188ms	50	50	100.00
		hmac_back_pressure	2.027m	4.019ms	50	50	100.00
		hmac_datapath_stress	23.186m	7.289ms	50	50	100.00
		hmac_burst_wr	1.159m	3.808ms	49	50	98.00
		hmac_error	4.370m	245.759ms	50	50	100.00
		hmac_wipe_secret	2.206m	12.169ms	50	50	100.00
		hmac_test_sha256_vectors	11.583m	164.703ms	5	5	100.00
		hmac_test_sha384_vectors	41.599m	240.634ms	5	5	100.00
		hmac_test_sha512_vectors	43.563m	885.358ms	5	5	100.00
		hmac_test_hmac256_vectors	1.199m	12.344ms	5	5	100.00
		hmac_test_hmac384_vectors	1.480m	5.596ms	5	5	100.00
		hmac_test_hmac512_vectors	2.181m	7.627ms	5	5	100.00
		hmac_stress_all	45.706m	78.863ms	50	50	100.00
V2	stress_all	hmac_stress_all	45.706m	78.863ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.660s	18.874us	50	50	100.00
V2	intr_test	hmac_intr_test	0.660s	55.471us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.360s	989.594us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.360s	989.594us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.020s	182.516us	5	5	100.00
		hmac_csr_rw	1.020s	20.598us	20	20	100.00
		hmac_csr_aliasing	8.710s	555.476us	5	5	100.00
		hmac_same_csr_outstanding	2.340s	149.915us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.020s	182.516us	5	5	100.00
		hmac_csr_rw	1.020s	20.598us	20	20	100.00
		hmac_csr_aliasing	8.710s	555.476us	5	5	100.00
		hmac_same_csr_outstanding	2.340s	149.915us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.170s	973.719us	5	5	100.00
		hmac_tl_intg_err	4.750s	363.320us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.750s	363.320us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.050s	2.766ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.197h	415.770ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			659	660	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.03	95.40	97.17	100.00	97.06	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:
  • Test hmac_burst_wr has 1 failures.

    • 41.hmac_burst_wr.115439692949331901096949052462484995487027349813075291196049189195760285264511
      Line 603, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/41.hmac_burst_wr/latest/run.log

        UVM_ERROR @ 595934159 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 595934159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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