HMAC Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.340s	951.857us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.990s	179.778us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.940s	110.532us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.640s	308.445us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.960s	1.074ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	15.982m	98.314ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.940s	110.532us	20	20	100.00
		hmac_csr_aliasing	8.960s	1.074ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.489m	14.556ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.928m	6.931ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.770m	421.169ms	5	5	100.00
		hmac_test_sha384_vectors	38.750m	473.330ms	5	5	100.00
		hmac_test_sha512_vectors	42.255m	836.458ms	4	5	80.00
		hmac_test_hmac256_vectors	1.165m	1.659ms	5	5	100.00
		hmac_test_hmac384_vectors	1.567m	11.340ms	5	5	100.00
		hmac_test_hmac512_vectors	2.264m	8.612ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.224m	5.441ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	24.619m	34.363ms	50	50	100.00
V2	error	hmac_error	5.198m	36.863ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.524m	15.980ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.340s	951.857us	50	50	100.00
		hmac_long_msg	4.489m	14.556ms	50	50	100.00
		hmac_back_pressure	1.928m	6.931ms	50	50	100.00
		hmac_datapath_stress	24.619m	34.363ms	50	50	100.00
		hmac_burst_wr	1.224m	5.441ms	49	50	98.00
		hmac_stress_all	1.488h	127.153ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.340s	951.857us	50	50	100.00
		hmac_long_msg	4.489m	14.556ms	50	50	100.00
		hmac_back_pressure	1.928m	6.931ms	50	50	100.00
		hmac_datapath_stress	24.619m	34.363ms	50	50	100.00
		hmac_wipe_secret	2.524m	15.980ms	50	50	100.00
		hmac_test_sha256_vectors	11.770m	421.169ms	5	5	100.00
		hmac_test_sha384_vectors	38.750m	473.330ms	5	5	100.00
		hmac_test_sha512_vectors	42.255m	836.458ms	4	5	80.00
		hmac_test_hmac256_vectors	1.165m	1.659ms	5	5	100.00
		hmac_test_hmac384_vectors	1.567m	11.340ms	5	5	100.00
		hmac_test_hmac512_vectors	2.264m	8.612ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.340s	951.857us	50	50	100.00
		hmac_long_msg	4.489m	14.556ms	50	50	100.00
		hmac_back_pressure	1.928m	6.931ms	50	50	100.00
		hmac_datapath_stress	24.619m	34.363ms	50	50	100.00
		hmac_burst_wr	1.224m	5.441ms	49	50	98.00
		hmac_error	5.198m	36.863ms	50	50	100.00
		hmac_wipe_secret	2.524m	15.980ms	50	50	100.00
		hmac_test_sha256_vectors	11.770m	421.169ms	5	5	100.00
		hmac_test_sha384_vectors	38.750m	473.330ms	5	5	100.00
		hmac_test_sha512_vectors	42.255m	836.458ms	4	5	80.00
		hmac_test_hmac256_vectors	1.165m	1.659ms	5	5	100.00
		hmac_test_hmac384_vectors	1.567m	11.340ms	5	5	100.00
		hmac_test_hmac512_vectors	2.264m	8.612ms	5	5	100.00
		hmac_stress_all	1.488h	127.153ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.488h	127.153ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.640s	17.080us	50	50	100.00
V2	intr_test	hmac_intr_test	0.670s	19.445us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.340s	289.405us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.340s	289.405us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.990s	179.778us	5	5	100.00
		hmac_csr_rw	0.940s	110.532us	20	20	100.00
		hmac_csr_aliasing	8.960s	1.074ms	5	5	100.00
		hmac_same_csr_outstanding	2.290s	521.041us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.990s	179.778us	5	5	100.00
		hmac_csr_rw	0.940s	110.532us	20	20	100.00
		hmac_csr_aliasing	8.960s	1.074ms	5	5	100.00
		hmac_same_csr_outstanding	2.290s	521.041us	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	1.020s	83.947us	5	5	100.00
		hmac_tl_intg_err	4.620s	1.200ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.620s	1.200ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.340s	951.857us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.972h	211.627ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			658	660	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.04	95.40	97.22	100.00	97.06	98.27	98.48	99.85

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test hmac_test_sha512_vectors has 1 failures.

    • 2.hmac_test_sha512_vectors.12990319312065034492200988906644422923297938225844081180798656006145320085358
      Line 245708, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest/run.log

        UVM_FATAL @ 3500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 3500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:

  • Test hmac_burst_wr has 1 failures.

    • 41.hmac_burst_wr.100171780820578669050137731424353807183522938331896536585075888675446210361098
      Line 384, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/41.hmac_burst_wr/latest/run.log

        UVM_ERROR @ 378074725 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 378074725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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