HMAC Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	15.840s	915.260us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.890s	286.668us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.970s	38.491us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.950s	1.730ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.940s	1.147ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	16.688m	279.184ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.970s	38.491us	20	20	100.00
		hmac_csr_aliasing	8.940s	1.147ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.883m	36.955ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	2.011m	3.952ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.942m	48.476ms	5	5	100.00
		hmac_test_sha384_vectors	42.330m	811.562ms	5	5	100.00
		hmac_test_sha512_vectors	41.407m	576.924ms	5	5	100.00
		hmac_test_hmac256_vectors	1.359m	15.817ms	5	5	100.00
		hmac_test_hmac384_vectors	1.622m	6.187ms	5	5	100.00
		hmac_test_hmac512_vectors	2.165m	16.692ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.441m	9.261ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	23.344m	15.066ms	50	50	100.00
V2	error	hmac_error	3.869m	75.235ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.411m	11.474ms	50	50	100.00
V2	save_and_restore	hmac_smoke	15.840s	915.260us	50	50	100.00
		hmac_long_msg	3.883m	36.955ms	50	50	100.00
		hmac_back_pressure	2.011m	3.952ms	50	50	100.00
		hmac_datapath_stress	23.344m	15.066ms	50	50	100.00
		hmac_burst_wr	1.441m	9.261ms	50	50	100.00
		hmac_stress_all	1.010h	124.182ms	49	50	98.00
V2	fifo_empty_status_interrupt	hmac_smoke	15.840s	915.260us	50	50	100.00
		hmac_long_msg	3.883m	36.955ms	50	50	100.00
		hmac_back_pressure	2.011m	3.952ms	50	50	100.00
		hmac_datapath_stress	23.344m	15.066ms	50	50	100.00
		hmac_wipe_secret	2.411m	11.474ms	50	50	100.00
		hmac_test_sha256_vectors	10.942m	48.476ms	5	5	100.00
		hmac_test_sha384_vectors	42.330m	811.562ms	5	5	100.00
		hmac_test_sha512_vectors	41.407m	576.924ms	5	5	100.00
		hmac_test_hmac256_vectors	1.359m	15.817ms	5	5	100.00
		hmac_test_hmac384_vectors	1.622m	6.187ms	5	5	100.00
		hmac_test_hmac512_vectors	2.165m	16.692ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	15.840s	915.260us	50	50	100.00
		hmac_long_msg	3.883m	36.955ms	50	50	100.00
		hmac_back_pressure	2.011m	3.952ms	50	50	100.00
		hmac_datapath_stress	23.344m	15.066ms	50	50	100.00
		hmac_burst_wr	1.441m	9.261ms	50	50	100.00
		hmac_error	3.869m	75.235ms	50	50	100.00
		hmac_wipe_secret	2.411m	11.474ms	50	50	100.00
		hmac_test_sha256_vectors	10.942m	48.476ms	5	5	100.00
		hmac_test_sha384_vectors	42.330m	811.562ms	5	5	100.00
		hmac_test_sha512_vectors	41.407m	576.924ms	5	5	100.00
		hmac_test_hmac256_vectors	1.359m	15.817ms	5	5	100.00
		hmac_test_hmac384_vectors	1.622m	6.187ms	5	5	100.00
		hmac_test_hmac512_vectors	2.165m	16.692ms	5	5	100.00
		hmac_stress_all	1.010h	124.182ms	49	50	98.00
V2	stress_all	hmac_stress_all	1.010h	124.182ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.650s	60.934us	50	50	100.00
V2	intr_test	hmac_intr_test	0.690s	16.895us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.020s	220.254us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.020s	220.254us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.890s	286.668us	5	5	100.00
		hmac_csr_rw	0.970s	38.491us	20	20	100.00
		hmac_csr_aliasing	8.940s	1.147ms	5	5	100.00
		hmac_same_csr_outstanding	2.370s	563.093us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.890s	286.668us	5	5	100.00
		hmac_csr_rw	0.970s	38.491us	20	20	100.00
		hmac_csr_aliasing	8.940s	1.147ms	5	5	100.00
		hmac_same_csr_outstanding	2.370s	563.093us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.010s	91.928us	5	5	100.00
		hmac_tl_intg_err	4.720s	576.012us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.720s	576.012us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	15.840s	915.260us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.153h	43.838ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			658	660	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.45	95.40	97.17	100.00	100.00	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 2 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 6.hmac_stress_all_with_rand_reset.35950894256798789970693585656182253946454149334820903464753187242930824414669
      Line 243942, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 40937745518 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 40937745518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test hmac_stress_all has 1 failures.

    • 13.hmac_stress_all.10932056192721871792918489999098359244560077960496156275506961415902688741615
      Line 25158, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_stress_all/latest/run.log

        UVM_ERROR @ 5630392738 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 5630392738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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