HMAC Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.750s	1.841ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.910s	131.248us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.970s	230.815us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.380s	2.925ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.880s	310.761us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	12.868m	1.277s	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.970s	230.815us	20	20	100.00
		hmac_csr_aliasing	7.880s	310.761us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.385m	11.203ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.844m	1.990ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.531m	174.241ms	5	5	100.00
		hmac_test_sha384_vectors	41.630m	148.710ms	5	5	100.00
		hmac_test_sha512_vectors	42.002m	144.611ms	5	5	100.00
		hmac_test_hmac256_vectors	1.203m	1.745ms	5	5	100.00
		hmac_test_hmac384_vectors	1.904m	39.764ms	5	5	100.00
		hmac_test_hmac512_vectors	2.239m	19.778ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.546m	26.900ms	47	50	94.00
V2	datapath_stress	hmac_datapath_stress	22.070m	30.526ms	50	50	100.00
V2	error	hmac_error	4.591m	66.514ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.547m	15.206ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.750s	1.841ms	50	50	100.00
		hmac_long_msg	3.385m	11.203ms	50	50	100.00
		hmac_back_pressure	1.844m	1.990ms	50	50	100.00
		hmac_datapath_stress	22.070m	30.526ms	50	50	100.00
		hmac_burst_wr	1.546m	26.900ms	47	50	94.00
		hmac_stress_all	1.398h	143.270ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.750s	1.841ms	50	50	100.00
		hmac_long_msg	3.385m	11.203ms	50	50	100.00
		hmac_back_pressure	1.844m	1.990ms	50	50	100.00
		hmac_datapath_stress	22.070m	30.526ms	50	50	100.00
		hmac_wipe_secret	2.547m	15.206ms	50	50	100.00
		hmac_test_sha256_vectors	10.531m	174.241ms	5	5	100.00
		hmac_test_sha384_vectors	41.630m	148.710ms	5	5	100.00
		hmac_test_sha512_vectors	42.002m	144.611ms	5	5	100.00
		hmac_test_hmac256_vectors	1.203m	1.745ms	5	5	100.00
		hmac_test_hmac384_vectors	1.904m	39.764ms	5	5	100.00
		hmac_test_hmac512_vectors	2.239m	19.778ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.750s	1.841ms	50	50	100.00
		hmac_long_msg	3.385m	11.203ms	50	50	100.00
		hmac_back_pressure	1.844m	1.990ms	50	50	100.00
		hmac_datapath_stress	22.070m	30.526ms	50	50	100.00
		hmac_burst_wr	1.546m	26.900ms	47	50	94.00
		hmac_error	4.591m	66.514ms	50	50	100.00
		hmac_wipe_secret	2.547m	15.206ms	50	50	100.00
		hmac_test_sha256_vectors	10.531m	174.241ms	5	5	100.00
		hmac_test_sha384_vectors	41.630m	148.710ms	5	5	100.00
		hmac_test_sha512_vectors	42.002m	144.611ms	5	5	100.00
		hmac_test_hmac256_vectors	1.203m	1.745ms	5	5	100.00
		hmac_test_hmac384_vectors	1.904m	39.764ms	5	5	100.00
		hmac_test_hmac512_vectors	2.239m	19.778ms	5	5	100.00
		hmac_stress_all	1.398h	143.270ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.398h	143.270ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.650s	25.927us	50	50	100.00
V2	intr_test	hmac_intr_test	0.640s	59.081us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.750s	851.247us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.750s	851.247us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.910s	131.248us	5	5	100.00
		hmac_csr_rw	0.970s	230.815us	20	20	100.00
		hmac_csr_aliasing	7.880s	310.761us	5	5	100.00
		hmac_same_csr_outstanding	2.630s	322.312us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.910s	131.248us	5	5	100.00
		hmac_csr_rw	0.970s	230.815us	20	20	100.00
		hmac_csr_aliasing	7.880s	310.761us	5	5	100.00
		hmac_same_csr_outstanding	2.630s	322.312us	20	20	100.00
V2		TOTAL			517	520	99.42
V2S	tl_intg_err	hmac_sec_cm	0.970s	81.749us	5	5	100.00
		hmac_tl_intg_err	4.880s	638.355us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.880s	638.355us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.750s	1.841ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.697h	419.880ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			657	660	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	95.40	97.22	100.00	94.12	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 3 failures:
  • Test hmac_burst_wr has 3 failures.

    • 14.hmac_burst_wr.88794301761973176471704456824330209235869642995334140286182171172582053616305
      Line 306, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_burst_wr/latest/run.log

        UVM_ERROR @ 112646928 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 112646928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.hmac_burst_wr.59925476518844354618630054891097898599349832506114292398772591653148472603359
      Line 680, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/30.hmac_burst_wr/latest/run.log

        UVM_ERROR @ 865554727 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 865554727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

Past Results

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