HMAC Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: e4c5daa580

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 16.010s 1.237ms 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.010s 39.227us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.970s 107.390us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.260s 4.389ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 5.550s 108.214us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 18.118m 73.474ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.970s 107.390us 20 20 100.00
hmac_csr_aliasing 5.550s 108.214us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 3.339m 55.289ms 50 50 100.00
V2 back_pressure hmac_back_pressure 2.176m 8.236ms 50 50 100.00
V2 test_vectors hmac_test_sha256_vectors 11.968m 109.036ms 5 5 100.00
hmac_test_sha384_vectors 44.041m 212.402ms 5 5 100.00
hmac_test_sha512_vectors 42.753m 412.295ms 5 5 100.00
hmac_test_hmac256_vectors 1.152m 5.858ms 5 5 100.00
hmac_test_hmac384_vectors 1.817m 13.019ms 5 5 100.00
hmac_test_hmac512_vectors 1.542m 7.829ms 5 5 100.00
V2 burst_wr hmac_burst_wr 1.112m 13.992ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 29.306m 15.052ms 50 50 100.00
V2 error hmac_error 5.097m 45.303ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 2.618m 11.669ms 50 50 100.00
V2 save_and_restore hmac_smoke 16.010s 1.237ms 50 50 100.00
hmac_long_msg 3.339m 55.289ms 50 50 100.00
hmac_back_pressure 2.176m 8.236ms 50 50 100.00
hmac_datapath_stress 29.306m 15.052ms 50 50 100.00
hmac_burst_wr 1.112m 13.992ms 50 50 100.00
hmac_stress_all 1.369h 115.311ms 50 50 100.00
V2 fifo_empty_status_interrupt hmac_smoke 16.010s 1.237ms 50 50 100.00
hmac_long_msg 3.339m 55.289ms 50 50 100.00
hmac_back_pressure 2.176m 8.236ms 50 50 100.00
hmac_datapath_stress 29.306m 15.052ms 50 50 100.00
hmac_wipe_secret 2.618m 11.669ms 50 50 100.00
hmac_test_sha256_vectors 11.968m 109.036ms 5 5 100.00
hmac_test_sha384_vectors 44.041m 212.402ms 5 5 100.00
hmac_test_sha512_vectors 42.753m 412.295ms 5 5 100.00
hmac_test_hmac256_vectors 1.152m 5.858ms 5 5 100.00
hmac_test_hmac384_vectors 1.817m 13.019ms 5 5 100.00
hmac_test_hmac512_vectors 1.542m 7.829ms 5 5 100.00
V2 wide_digest_configurable_key_length hmac_smoke 16.010s 1.237ms 50 50 100.00
hmac_long_msg 3.339m 55.289ms 50 50 100.00
hmac_back_pressure 2.176m 8.236ms 50 50 100.00
hmac_datapath_stress 29.306m 15.052ms 50 50 100.00
hmac_burst_wr 1.112m 13.992ms 50 50 100.00
hmac_error 5.097m 45.303ms 50 50 100.00
hmac_wipe_secret 2.618m 11.669ms 50 50 100.00
hmac_test_sha256_vectors 11.968m 109.036ms 5 5 100.00
hmac_test_sha384_vectors 44.041m 212.402ms 5 5 100.00
hmac_test_sha512_vectors 42.753m 412.295ms 5 5 100.00
hmac_test_hmac256_vectors 1.152m 5.858ms 5 5 100.00
hmac_test_hmac384_vectors 1.817m 13.019ms 5 5 100.00
hmac_test_hmac512_vectors 1.542m 7.829ms 5 5 100.00
hmac_stress_all 1.369h 115.311ms 50 50 100.00
V2 stress_all hmac_stress_all 1.369h 115.311ms 50 50 100.00
V2 alert_test hmac_alert_test 0.630s 50.087us 50 50 100.00
V2 intr_test hmac_intr_test 0.690s 17.045us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.510s 1.010ms 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.510s 1.010ms 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.010s 39.227us 5 5 100.00
hmac_csr_rw 0.970s 107.390us 20 20 100.00
hmac_csr_aliasing 5.550s 108.214us 5 5 100.00
hmac_same_csr_outstanding 2.510s 299.002us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.010s 39.227us 5 5 100.00
hmac_csr_rw 0.970s 107.390us 20 20 100.00
hmac_csr_aliasing 5.550s 108.214us 5 5 100.00
hmac_same_csr_outstanding 2.510s 299.002us 20 20 100.00
V2 TOTAL 520 520 100.00
V2S tl_intg_err hmac_sec_cm 1.060s 100.111us 5 5 100.00
hmac_tl_intg_err 4.330s 1.001ms 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.330s 1.001ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 16.010s 1.237ms 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.057h 201.381ms 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 660 660 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.46 95.40 97.22 100.00 100.00 98.27 98.48 99.85

Past Results