HMAC Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.200s	5.233ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.970s	132.867us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.900s	18.996us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	10.920s	1.936ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.190s	1.228ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	17.481m	222.408ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.900s	18.996us	20	20	100.00
		hmac_csr_aliasing	9.190s	1.228ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.588m	62.917ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.638m	6.046ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	10.793m	37.004ms	5	5	100.00
		hmac_test_sha384_vectors	43.505m	435.353ms	5	5	100.00
		hmac_test_sha512_vectors	42.767m	417.837ms	5	5	100.00
		hmac_test_hmac256_vectors	1.211m	4.793ms	5	5	100.00
		hmac_test_hmac384_vectors	1.743m	9.640ms	5	5	100.00
		hmac_test_hmac512_vectors	2.397m	14.411ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.336m	4.251ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	27.561m	27.054ms	50	50	100.00
V2	error	hmac_error	4.734m	10.099ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.490m	16.659ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.200s	5.233ms	50	50	100.00
		hmac_long_msg	3.588m	62.917ms	50	50	100.00
		hmac_back_pressure	1.638m	6.046ms	50	50	100.00
		hmac_datapath_stress	27.561m	27.054ms	50	50	100.00
		hmac_burst_wr	1.336m	4.251ms	49	50	98.00
		hmac_stress_all	1.372h	84.190ms	49	50	98.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.200s	5.233ms	50	50	100.00
		hmac_long_msg	3.588m	62.917ms	50	50	100.00
		hmac_back_pressure	1.638m	6.046ms	50	50	100.00
		hmac_datapath_stress	27.561m	27.054ms	50	50	100.00
		hmac_wipe_secret	2.490m	16.659ms	50	50	100.00
		hmac_test_sha256_vectors	10.793m	37.004ms	5	5	100.00
		hmac_test_sha384_vectors	43.505m	435.353ms	5	5	100.00
		hmac_test_sha512_vectors	42.767m	417.837ms	5	5	100.00
		hmac_test_hmac256_vectors	1.211m	4.793ms	5	5	100.00
		hmac_test_hmac384_vectors	1.743m	9.640ms	5	5	100.00
		hmac_test_hmac512_vectors	2.397m	14.411ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.200s	5.233ms	50	50	100.00
		hmac_long_msg	3.588m	62.917ms	50	50	100.00
		hmac_back_pressure	1.638m	6.046ms	50	50	100.00
		hmac_datapath_stress	27.561m	27.054ms	50	50	100.00
		hmac_burst_wr	1.336m	4.251ms	49	50	98.00
		hmac_error	4.734m	10.099ms	50	50	100.00
		hmac_wipe_secret	2.490m	16.659ms	50	50	100.00
		hmac_test_sha256_vectors	10.793m	37.004ms	5	5	100.00
		hmac_test_sha384_vectors	43.505m	435.353ms	5	5	100.00
		hmac_test_sha512_vectors	42.767m	417.837ms	5	5	100.00
		hmac_test_hmac256_vectors	1.211m	4.793ms	5	5	100.00
		hmac_test_hmac384_vectors	1.743m	9.640ms	5	5	100.00
		hmac_test_hmac512_vectors	2.397m	14.411ms	5	5	100.00
		hmac_stress_all	1.372h	84.190ms	49	50	98.00
V2	stress_all	hmac_stress_all	1.372h	84.190ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.640s	14.222us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	105.602us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.590s	162.520us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.590s	162.520us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.970s	132.867us	5	5	100.00
		hmac_csr_rw	0.900s	18.996us	20	20	100.00
		hmac_csr_aliasing	9.190s	1.228ms	5	5	100.00
		hmac_same_csr_outstanding	2.380s	1.792ms	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.970s	132.867us	5	5	100.00
		hmac_csr_rw	0.900s	18.996us	20	20	100.00
		hmac_csr_aliasing	9.190s	1.228ms	5	5	100.00
		hmac_same_csr_outstanding	2.380s	1.792ms	20	20	100.00
V2		TOTAL			518	520	99.62
V2S	tl_intg_err	hmac_sec_cm	0.900s	57.670us	5	5	100.00
		hmac_tl_intg_err	4.410s	286.003us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.410s	286.003us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.200s	5.233ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.718h	404.192ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			657	660	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.03	95.40	97.17	100.00	97.06	98.27	98.48	99.85

Failure Buckets

UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 3 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 4.hmac_stress_all_with_rand_reset.88334728978775648908696396729393746275012478480976214059504405917197432600082
    Line 429441, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43938076593 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 43938076593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_stress_all has 1 failures.
  - 25.hmac_stress_all.64017202440550737074392220105165938842550475226786087945613799135227441399681
    Line 222122, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/25.hmac_stress_all/latest/run.log
```
  UVM_ERROR @ 83522692693 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 83522692693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test hmac_burst_wr has 1 failures.
  - 29.hmac_burst_wr.105969507492242046204857681517585154013359623825207419515116256502327329406962
    Line 743, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/29.hmac_burst_wr/latest/run.log
```
  UVM_ERROR @ 2674880193 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
  UVM_INFO @ 2674880193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: 5fd4ecc0fc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `5fd4ecc0fc`