HMAC Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: bbf435ceff

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	15.080s	317.419us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.990s	156.680us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.970s	30.043us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	14.950s	5.211ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	5.500s	575.684us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	5.541m	156.878ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.970s	30.043us	20	20	100.00
		hmac_csr_aliasing	5.500s	575.684us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	4.057m	53.307ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.747m	1.800ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.556m	111.569ms	5	5	100.00
		hmac_test_sha384_vectors	46.273m	917.255ms	5	5	100.00
		hmac_test_sha512_vectors	43.753m	786.605ms	5	5	100.00
		hmac_test_hmac256_vectors	50.040s	15.849ms	5	5	100.00
		hmac_test_hmac384_vectors	1.134m	4.375ms	5	5	100.00
		hmac_test_hmac512_vectors	2.381m	12.472ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.315m	9.414ms	49	50	98.00
V2	datapath_stress	hmac_datapath_stress	32.599m	18.419ms	50	50	100.00
V2	error	hmac_error	4.774m	35.702ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.604m	11.955ms	50	50	100.00
V2	save_and_restore	hmac_smoke	15.080s	317.419us	50	50	100.00
		hmac_long_msg	4.057m	53.307ms	50	50	100.00
		hmac_back_pressure	1.747m	1.800ms	50	50	100.00
		hmac_datapath_stress	32.599m	18.419ms	50	50	100.00
		hmac_burst_wr	1.315m	9.414ms	49	50	98.00
		hmac_stress_all	1.381h	123.909ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	15.080s	317.419us	50	50	100.00
		hmac_long_msg	4.057m	53.307ms	50	50	100.00
		hmac_back_pressure	1.747m	1.800ms	50	50	100.00
		hmac_datapath_stress	32.599m	18.419ms	50	50	100.00
		hmac_wipe_secret	2.604m	11.955ms	50	50	100.00
		hmac_test_sha256_vectors	11.556m	111.569ms	5	5	100.00
		hmac_test_sha384_vectors	46.273m	917.255ms	5	5	100.00
		hmac_test_sha512_vectors	43.753m	786.605ms	5	5	100.00
		hmac_test_hmac256_vectors	50.040s	15.849ms	5	5	100.00
		hmac_test_hmac384_vectors	1.134m	4.375ms	5	5	100.00
		hmac_test_hmac512_vectors	2.381m	12.472ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	15.080s	317.419us	50	50	100.00
		hmac_long_msg	4.057m	53.307ms	50	50	100.00
		hmac_back_pressure	1.747m	1.800ms	50	50	100.00
		hmac_datapath_stress	32.599m	18.419ms	50	50	100.00
		hmac_burst_wr	1.315m	9.414ms	49	50	98.00
		hmac_error	4.774m	35.702ms	50	50	100.00
		hmac_wipe_secret	2.604m	11.955ms	50	50	100.00
		hmac_test_sha256_vectors	11.556m	111.569ms	5	5	100.00
		hmac_test_sha384_vectors	46.273m	917.255ms	5	5	100.00
		hmac_test_sha512_vectors	43.753m	786.605ms	5	5	100.00
		hmac_test_hmac256_vectors	50.040s	15.849ms	5	5	100.00
		hmac_test_hmac384_vectors	1.134m	4.375ms	5	5	100.00
		hmac_test_hmac512_vectors	2.381m	12.472ms	5	5	100.00
		hmac_stress_all	1.381h	123.909ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.381h	123.909ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.680s	15.739us	50	50	100.00
V2	intr_test	hmac_intr_test	0.670s	50.746us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.220s	215.354us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.220s	215.354us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.990s	156.680us	5	5	100.00
		hmac_csr_rw	0.970s	30.043us	20	20	100.00
		hmac_csr_aliasing	5.500s	575.684us	5	5	100.00
		hmac_same_csr_outstanding	2.310s	2.030ms	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.990s	156.680us	5	5	100.00
		hmac_csr_rw	0.970s	30.043us	20	20	100.00
		hmac_csr_aliasing	5.500s	575.684us	5	5	100.00
		hmac_same_csr_outstanding	2.310s	2.030ms	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	1.140s	253.360us	5	5	100.00
		hmac_tl_intg_err	4.580s	349.555us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.580s	349.555us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	15.080s	317.419us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	2.551h	1.245s	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			659	660	99.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.03	95.40	97.17	100.00	97.06	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 1 failures:
  • Test hmac_burst_wr has 1 failures.

    • 27.hmac_burst_wr.65033802738194963404845231712787296702671613435996286486069039816737109231137
      Line 524, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/27.hmac_burst_wr/latest/run.log

        UVM_ERROR @ 1336167805 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 1336167805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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