HMAC Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.030s	997.087us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.060s	128.487us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.980s	303.368us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.670s	1.611ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.100s	461.559us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	19.366m	469.722ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.980s	303.368us	20	20	100.00
		hmac_csr_aliasing	9.100s	461.559us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	3.612m	16.452ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.743m	9.740ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	11.066m	103.905ms	5	5	100.00
		hmac_test_sha384_vectors	45.410m	223.650ms	5	5	100.00
		hmac_test_sha512_vectors	39.263m	218.520ms	5	5	100.00
		hmac_test_hmac256_vectors	1.068m	61.849ms	5	5	100.00
		hmac_test_hmac384_vectors	1.628m	6.826ms	5	5	100.00
		hmac_test_hmac512_vectors	2.322m	109.741ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	1.129m	5.114ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	32.223m	32.366ms	50	50	100.00
V2	error	hmac_error	4.136m	40.863ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.392m	31.595ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.030s	997.087us	50	50	100.00
		hmac_long_msg	3.612m	16.452ms	50	50	100.00
		hmac_back_pressure	1.743m	9.740ms	50	50	100.00
		hmac_datapath_stress	32.223m	32.366ms	50	50	100.00
		hmac_burst_wr	1.129m	5.114ms	50	50	100.00
		hmac_stress_all	39.706m	427.672ms	49	50	98.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.030s	997.087us	50	50	100.00
		hmac_long_msg	3.612m	16.452ms	50	50	100.00
		hmac_back_pressure	1.743m	9.740ms	50	50	100.00
		hmac_datapath_stress	32.223m	32.366ms	50	50	100.00
		hmac_wipe_secret	2.392m	31.595ms	50	50	100.00
		hmac_test_sha256_vectors	11.066m	103.905ms	5	5	100.00
		hmac_test_sha384_vectors	45.410m	223.650ms	5	5	100.00
		hmac_test_sha512_vectors	39.263m	218.520ms	5	5	100.00
		hmac_test_hmac256_vectors	1.068m	61.849ms	5	5	100.00
		hmac_test_hmac384_vectors	1.628m	6.826ms	5	5	100.00
		hmac_test_hmac512_vectors	2.322m	109.741ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.030s	997.087us	50	50	100.00
		hmac_long_msg	3.612m	16.452ms	50	50	100.00
		hmac_back_pressure	1.743m	9.740ms	50	50	100.00
		hmac_datapath_stress	32.223m	32.366ms	50	50	100.00
		hmac_burst_wr	1.129m	5.114ms	50	50	100.00
		hmac_error	4.136m	40.863ms	50	50	100.00
		hmac_wipe_secret	2.392m	31.595ms	50	50	100.00
		hmac_test_sha256_vectors	11.066m	103.905ms	5	5	100.00
		hmac_test_sha384_vectors	45.410m	223.650ms	5	5	100.00
		hmac_test_sha512_vectors	39.263m	218.520ms	5	5	100.00
		hmac_test_hmac256_vectors	1.068m	61.849ms	5	5	100.00
		hmac_test_hmac384_vectors	1.628m	6.826ms	5	5	100.00
		hmac_test_hmac512_vectors	2.322m	109.741ms	5	5	100.00
		hmac_stress_all	39.706m	427.672ms	49	50	98.00
V2	stress_all	hmac_stress_all	39.706m	427.672ms	49	50	98.00
V2	alert_test	hmac_alert_test	0.640s	45.111us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	149.817us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.440s	1.659ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.440s	1.659ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.060s	128.487us	5	5	100.00
		hmac_csr_rw	0.980s	303.368us	20	20	100.00
		hmac_csr_aliasing	9.100s	461.559us	5	5	100.00
		hmac_same_csr_outstanding	2.420s	285.137us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.060s	128.487us	5	5	100.00
		hmac_csr_rw	0.980s	303.368us	20	20	100.00
		hmac_csr_aliasing	9.100s	461.559us	5	5	100.00
		hmac_same_csr_outstanding	2.420s	285.137us	20	20	100.00
V2		TOTAL			519	520	99.81
V2S	tl_intg_err	hmac_sec_cm	0.970s	62.110us	5	5	100.00
		hmac_tl_intg_err	4.570s	1.106ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.570s	1.106ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.030s	997.087us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.093h	836.750ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			658	660	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.46	95.40	97.22	100.00	100.00	98.27	98.48	99.85

Failure Buckets

• UVM_ERROR (hmac_scoreboard.sv:481) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) intr_state` has 2 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 2.hmac_stress_all_with_rand_reset.26689423833588711343133213206951738604009959505388617570250892088340360128680
      Line 286284, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 528725196769 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 528725196769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test hmac_stress_all has 1 failures.

    • 17.hmac_stress_all.71266070201565906624774096532164578807522527663080014263150312560426406134242
      Line 12771, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_stress_all/latest/run.log

        UVM_ERROR @ 11997164636 ps: (hmac_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 2 [0x2]) intr_state
        UVM_INFO @ 11997164636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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